1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m528x.c -- platform support for ColdFire 528x based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Sub-architcture dependent initialization code for the Freescale
8*4882a593Smuzhiyun * 5280, 5281 and 5282 CPUs.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
11*4882a593Smuzhiyun * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /***************************************************************************/
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/param.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/io.h>
21*4882a593Smuzhiyun #include <asm/machdep.h>
22*4882a593Smuzhiyun #include <asm/coldfire.h>
23*4882a593Smuzhiyun #include <asm/mcfsim.h>
24*4882a593Smuzhiyun #include <asm/mcfuart.h>
25*4882a593Smuzhiyun #include <asm/mcfclk.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /***************************************************************************/
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
30*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
31*4882a593Smuzhiyun DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
32*4882a593Smuzhiyun DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
33*4882a593Smuzhiyun DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
34*4882a593Smuzhiyun DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
35*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
36*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
37*4882a593Smuzhiyun DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
38*4882a593Smuzhiyun DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
39*4882a593Smuzhiyun DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
40*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct clk *mcf_clks[] = {
43*4882a593Smuzhiyun &clk_pll,
44*4882a593Smuzhiyun &clk_sys,
45*4882a593Smuzhiyun &clk_mcfpit0,
46*4882a593Smuzhiyun &clk_mcfpit1,
47*4882a593Smuzhiyun &clk_mcfpit2,
48*4882a593Smuzhiyun &clk_mcfpit3,
49*4882a593Smuzhiyun &clk_mcfuart0,
50*4882a593Smuzhiyun &clk_mcfuart1,
51*4882a593Smuzhiyun &clk_mcfuart2,
52*4882a593Smuzhiyun &clk_mcfqspi0,
53*4882a593Smuzhiyun &clk_fec0,
54*4882a593Smuzhiyun &clk_mcfi2c0,
55*4882a593Smuzhiyun NULL
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /***************************************************************************/
59*4882a593Smuzhiyun
m528x_qspi_init(void)60*4882a593Smuzhiyun static void __init m528x_qspi_init(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
63*4882a593Smuzhiyun /* setup Port QS for QSPI with gpio CS control */
64*4882a593Smuzhiyun __raw_writeb(0x07, MCFGPIO_PQSPAR);
65*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /***************************************************************************/
69*4882a593Smuzhiyun
m528x_i2c_init(void)70*4882a593Smuzhiyun static void __init m528x_i2c_init(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
73*4882a593Smuzhiyun u16 paspar;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* setup Port AS Pin Assignment Register for I2C */
76*4882a593Smuzhiyun /* set PASPA0 to SCL and PASPA1 to SDA */
77*4882a593Smuzhiyun paspar = readw(MCFGPIO_PASPAR);
78*4882a593Smuzhiyun paspar |= 0xF;
79*4882a593Smuzhiyun writew(paspar, MCFGPIO_PASPAR);
80*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /***************************************************************************/
84*4882a593Smuzhiyun
m528x_uarts_init(void)85*4882a593Smuzhiyun static void __init m528x_uarts_init(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun u8 port;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* make sure PUAPAR is set for UART0 and UART1 */
90*4882a593Smuzhiyun port = readb(MCFGPIO_PUAPAR);
91*4882a593Smuzhiyun port |= 0x03 | (0x03 << 2);
92*4882a593Smuzhiyun writeb(port, MCFGPIO_PUAPAR);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /***************************************************************************/
96*4882a593Smuzhiyun
m528x_fec_init(void)97*4882a593Smuzhiyun static void __init m528x_fec_init(void)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun u16 v16;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Set multi-function pins to ethernet mode for fec0 */
102*4882a593Smuzhiyun v16 = readw(MCFGPIO_PASPAR);
103*4882a593Smuzhiyun writew(v16 | 0xf00, MCFGPIO_PASPAR);
104*4882a593Smuzhiyun writeb(0xc0, MCFGPIO_PEHLPAR);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /***************************************************************************/
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #ifdef CONFIG_WILDFIRE
wildfire_halt(void)110*4882a593Smuzhiyun void wildfire_halt(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun writeb(0, 0x30000007);
113*4882a593Smuzhiyun writeb(0x2, 0x30000007);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #ifdef CONFIG_WILDFIREMOD
wildfiremod_halt(void)118*4882a593Smuzhiyun void wildfiremod_halt(void)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun printk(KERN_INFO "WildFireMod hibernating...\n");
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* Set portE.5 to Digital IO */
123*4882a593Smuzhiyun writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Make portE.5 an output */
126*4882a593Smuzhiyun writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* Now toggle portE.5 from low to high */
129*4882a593Smuzhiyun writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
130*4882a593Smuzhiyun writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun printk(KERN_EMERG "Failed to hibernate. Halting!\n");
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun #endif
135*4882a593Smuzhiyun
config_BSP(char * commandp,int size)136*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun #ifdef CONFIG_WILDFIRE
139*4882a593Smuzhiyun mach_halt = wildfire_halt;
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun #ifdef CONFIG_WILDFIREMOD
142*4882a593Smuzhiyun mach_halt = wildfiremod_halt;
143*4882a593Smuzhiyun #endif
144*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
145*4882a593Smuzhiyun m528x_uarts_init();
146*4882a593Smuzhiyun m528x_fec_init();
147*4882a593Smuzhiyun m528x_qspi_init();
148*4882a593Smuzhiyun m528x_i2c_init();
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /***************************************************************************/
152