1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m527x.c -- platform support for ColdFire 527x based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Sub-architcture dependent initialization code for the Freescale
8*4882a593Smuzhiyun * 5270/5271 and 5274/5275 CPUs.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
11*4882a593Smuzhiyun * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /***************************************************************************/
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/param.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <asm/machdep.h>
21*4882a593Smuzhiyun #include <asm/coldfire.h>
22*4882a593Smuzhiyun #include <asm/mcfsim.h>
23*4882a593Smuzhiyun #include <asm/mcfuart.h>
24*4882a593Smuzhiyun #include <asm/mcfclk.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /***************************************************************************/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
29*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30*4882a593Smuzhiyun DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31*4882a593Smuzhiyun DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32*4882a593Smuzhiyun DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33*4882a593Smuzhiyun DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
34*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
35*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36*4882a593Smuzhiyun DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37*4882a593Smuzhiyun DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
38*4882a593Smuzhiyun DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
39*4882a593Smuzhiyun DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
40*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct clk *mcf_clks[] = {
43*4882a593Smuzhiyun &clk_pll,
44*4882a593Smuzhiyun &clk_sys,
45*4882a593Smuzhiyun &clk_mcfpit0,
46*4882a593Smuzhiyun &clk_mcfpit1,
47*4882a593Smuzhiyun &clk_mcfpit2,
48*4882a593Smuzhiyun &clk_mcfpit3,
49*4882a593Smuzhiyun &clk_mcfuart0,
50*4882a593Smuzhiyun &clk_mcfuart1,
51*4882a593Smuzhiyun &clk_mcfuart2,
52*4882a593Smuzhiyun &clk_mcfqspi0,
53*4882a593Smuzhiyun &clk_fec0,
54*4882a593Smuzhiyun &clk_fec1,
55*4882a593Smuzhiyun &clk_mcfi2c0,
56*4882a593Smuzhiyun NULL
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /***************************************************************************/
60*4882a593Smuzhiyun
m527x_qspi_init(void)61*4882a593Smuzhiyun static void __init m527x_qspi_init(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
64*4882a593Smuzhiyun #if defined(CONFIG_M5271)
65*4882a593Smuzhiyun u16 par;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* setup QSPS pins for QSPI with gpio CS control */
68*4882a593Smuzhiyun writeb(0x1f, MCFGPIO_PAR_QSPI);
69*4882a593Smuzhiyun /* and CS2 & CS3 as gpio */
70*4882a593Smuzhiyun par = readw(MCFGPIO_PAR_TIMER);
71*4882a593Smuzhiyun par &= 0x3f3f;
72*4882a593Smuzhiyun writew(par, MCFGPIO_PAR_TIMER);
73*4882a593Smuzhiyun #elif defined(CONFIG_M5275)
74*4882a593Smuzhiyun /* setup QSPS pins for QSPI with gpio CS control */
75*4882a593Smuzhiyun writew(0x003e, MCFGPIO_PAR_QSPI);
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /***************************************************************************/
81*4882a593Smuzhiyun
m527x_i2c_init(void)82*4882a593Smuzhiyun static void __init m527x_i2c_init(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
85*4882a593Smuzhiyun #if defined(CONFIG_M5271)
86*4882a593Smuzhiyun u8 par;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* setup Port FECI2C Pin Assignment Register for I2C */
89*4882a593Smuzhiyun /* set PAR_SCL to SCL and PAR_SDA to SDA */
90*4882a593Smuzhiyun par = readb(MCFGPIO_PAR_FECI2C);
91*4882a593Smuzhiyun par |= 0x0f;
92*4882a593Smuzhiyun writeb(par, MCFGPIO_PAR_FECI2C);
93*4882a593Smuzhiyun #elif defined(CONFIG_M5275)
94*4882a593Smuzhiyun u16 par;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* setup Port FECI2C Pin Assignment Register for I2C */
97*4882a593Smuzhiyun /* set PAR_SCL to SCL and PAR_SDA to SDA */
98*4882a593Smuzhiyun par = readw(MCFGPIO_PAR_FECI2C);
99*4882a593Smuzhiyun par |= 0x0f;
100*4882a593Smuzhiyun writew(par, MCFGPIO_PAR_FECI2C);
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /***************************************************************************/
106*4882a593Smuzhiyun
m527x_uarts_init(void)107*4882a593Smuzhiyun static void __init m527x_uarts_init(void)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun u16 sepmask;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun * External Pin Mask Setting & Enable External Pin for Interface
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun sepmask = readw(MCFGPIO_PAR_UART);
115*4882a593Smuzhiyun sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
116*4882a593Smuzhiyun writew(sepmask, MCFGPIO_PAR_UART);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /***************************************************************************/
120*4882a593Smuzhiyun
m527x_fec_init(void)121*4882a593Smuzhiyun static void __init m527x_fec_init(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun u8 v;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Set multi-function pins to ethernet mode for fec0 */
126*4882a593Smuzhiyun #if defined(CONFIG_M5271)
127*4882a593Smuzhiyun v = readb(MCFGPIO_PAR_FECI2C);
128*4882a593Smuzhiyun writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
129*4882a593Smuzhiyun #else
130*4882a593Smuzhiyun u16 par;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun par = readw(MCFGPIO_PAR_FECI2C);
133*4882a593Smuzhiyun writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
134*4882a593Smuzhiyun v = readb(MCFGPIO_PAR_FEC0HL);
135*4882a593Smuzhiyun writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Set multi-function pins to ethernet mode for fec1 */
138*4882a593Smuzhiyun par = readw(MCFGPIO_PAR_FECI2C);
139*4882a593Smuzhiyun writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
140*4882a593Smuzhiyun v = readb(MCFGPIO_PAR_FEC1HL);
141*4882a593Smuzhiyun writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
142*4882a593Smuzhiyun #endif
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /***************************************************************************/
146*4882a593Smuzhiyun
config_BSP(char * commandp,int size)147*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
150*4882a593Smuzhiyun m527x_uarts_init();
151*4882a593Smuzhiyun m527x_fec_init();
152*4882a593Smuzhiyun m527x_qspi_init();
153*4882a593Smuzhiyun m527x_i2c_init();
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /***************************************************************************/
157