1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m5272.c -- platform support for ColdFire 5272 based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
8*4882a593Smuzhiyun * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /***************************************************************************/
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/param.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/phy.h>
18*4882a593Smuzhiyun #include <linux/phy_fixed.h>
19*4882a593Smuzhiyun #include <asm/machdep.h>
20*4882a593Smuzhiyun #include <asm/coldfire.h>
21*4882a593Smuzhiyun #include <asm/mcfsim.h>
22*4882a593Smuzhiyun #include <asm/mcfuart.h>
23*4882a593Smuzhiyun #include <asm/mcfclk.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /***************************************************************************/
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * Some platforms need software versions of the GPIO data registers.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun unsigned short ppdata;
31*4882a593Smuzhiyun unsigned char ledbank = 0xff;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /***************************************************************************/
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
36*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
37*4882a593Smuzhiyun DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
38*4882a593Smuzhiyun DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
39*4882a593Smuzhiyun DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
40*4882a593Smuzhiyun DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
41*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
42*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
43*4882a593Smuzhiyun DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
44*4882a593Smuzhiyun DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct clk *mcf_clks[] = {
47*4882a593Smuzhiyun &clk_pll,
48*4882a593Smuzhiyun &clk_sys,
49*4882a593Smuzhiyun &clk_mcftmr0,
50*4882a593Smuzhiyun &clk_mcftmr1,
51*4882a593Smuzhiyun &clk_mcftmr2,
52*4882a593Smuzhiyun &clk_mcftmr3,
53*4882a593Smuzhiyun &clk_mcfuart0,
54*4882a593Smuzhiyun &clk_mcfuart1,
55*4882a593Smuzhiyun &clk_mcfqspi0,
56*4882a593Smuzhiyun &clk_fec0,
57*4882a593Smuzhiyun NULL
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /***************************************************************************/
61*4882a593Smuzhiyun
m5272_uarts_init(void)62*4882a593Smuzhiyun static void __init m5272_uarts_init(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun u32 v;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Enable the output lines for the serial ports */
67*4882a593Smuzhiyun v = readl(MCFSIM_PBCNT);
68*4882a593Smuzhiyun v = (v & ~0x000000ff) | 0x00000055;
69*4882a593Smuzhiyun writel(v, MCFSIM_PBCNT);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun v = readl(MCFSIM_PDCNT);
72*4882a593Smuzhiyun v = (v & ~0x000003fc) | 0x000002a8;
73*4882a593Smuzhiyun writel(v, MCFSIM_PDCNT);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /***************************************************************************/
77*4882a593Smuzhiyun
m5272_cpu_reset(void)78*4882a593Smuzhiyun static void m5272_cpu_reset(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun local_irq_disable();
81*4882a593Smuzhiyun /* Set watchdog to reset, and enabled */
82*4882a593Smuzhiyun __raw_writew(0, MCFSIM_WIRR);
83*4882a593Smuzhiyun __raw_writew(1, MCFSIM_WRRR);
84*4882a593Smuzhiyun __raw_writew(0, MCFSIM_WCR);
85*4882a593Smuzhiyun for (;;)
86*4882a593Smuzhiyun /* wait for watchdog to timeout */;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /***************************************************************************/
90*4882a593Smuzhiyun
config_BSP(char * commandp,int size)91*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun #if defined (CONFIG_MOD5272)
94*4882a593Smuzhiyun /* Set base of device vectors to be 64 */
95*4882a593Smuzhiyun writeb(0x40, MCFSIM_PIVR);
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
99*4882a593Smuzhiyun /* Copy command line from FLASH to local buffer... */
100*4882a593Smuzhiyun memcpy(commandp, (char *) 0xf0004000, size);
101*4882a593Smuzhiyun commandp[size-1] = 0;
102*4882a593Smuzhiyun #elif defined(CONFIG_CANCam)
103*4882a593Smuzhiyun /* Copy command line from FLASH to local buffer... */
104*4882a593Smuzhiyun memcpy(commandp, (char *) 0xf0010000, size);
105*4882a593Smuzhiyun commandp[size-1] = 0;
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun mach_reset = m5272_cpu_reset;
109*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /***************************************************************************/
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * Some 5272 based boards have the FEC ethernet directly connected to
116*4882a593Smuzhiyun * an ethernet switch. In this case we need to use the fixed phy type,
117*4882a593Smuzhiyun * and we need to declare it early in boot.
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
120*4882a593Smuzhiyun .link = 1,
121*4882a593Smuzhiyun .speed = 100,
122*4882a593Smuzhiyun .duplex = 0,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /***************************************************************************/
126*4882a593Smuzhiyun
init_BSP(void)127*4882a593Smuzhiyun static int __init init_BSP(void)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun m5272_uarts_init();
130*4882a593Smuzhiyun fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
131*4882a593Smuzhiyun return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun arch_initcall(init_BSP);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /***************************************************************************/
137