1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * 525x.c -- platform support for ColdFire 525x based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /***************************************************************************/
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/param.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <asm/machdep.h>
18*4882a593Smuzhiyun #include <asm/coldfire.h>
19*4882a593Smuzhiyun #include <asm/mcfsim.h>
20*4882a593Smuzhiyun #include <asm/mcfclk.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /***************************************************************************/
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
25*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
26*4882a593Smuzhiyun DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
27*4882a593Smuzhiyun DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
28*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
29*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
30*4882a593Smuzhiyun DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
31*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
32*4882a593Smuzhiyun DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct clk *mcf_clks[] = {
35*4882a593Smuzhiyun &clk_pll,
36*4882a593Smuzhiyun &clk_sys,
37*4882a593Smuzhiyun &clk_mcftmr0,
38*4882a593Smuzhiyun &clk_mcftmr1,
39*4882a593Smuzhiyun &clk_mcfuart0,
40*4882a593Smuzhiyun &clk_mcfuart1,
41*4882a593Smuzhiyun &clk_mcfqspi0,
42*4882a593Smuzhiyun &clk_mcfi2c0,
43*4882a593Smuzhiyun &clk_mcfi2c1,
44*4882a593Smuzhiyun NULL
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /***************************************************************************/
48*4882a593Smuzhiyun
m525x_qspi_init(void)49*4882a593Smuzhiyun static void __init m525x_qspi_init(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
52*4882a593Smuzhiyun /* set the GPIO function for the qspi cs gpios */
53*4882a593Smuzhiyun /* FIXME: replace with pinmux/pinctl support */
54*4882a593Smuzhiyun u32 f = readl(MCFSIM2_GPIOFUNC);
55*4882a593Smuzhiyun f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
56*4882a593Smuzhiyun writel(f, MCFSIM2_GPIOFUNC);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* QSPI irq setup */
59*4882a593Smuzhiyun writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
60*4882a593Smuzhiyun MCFSIM_QSPIICR);
61*4882a593Smuzhiyun mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
62*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
m525x_i2c_init(void)65*4882a593Smuzhiyun static void __init m525x_i2c_init(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
68*4882a593Smuzhiyun u32 r;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* first I2C controller uses regular irq setup */
71*4882a593Smuzhiyun writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
72*4882a593Smuzhiyun MCFSIM_I2CICR);
73*4882a593Smuzhiyun mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* second I2C controller is completely different */
76*4882a593Smuzhiyun r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
77*4882a593Smuzhiyun r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
78*4882a593Smuzhiyun r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
79*4882a593Smuzhiyun writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
80*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /***************************************************************************/
84*4882a593Smuzhiyun
config_BSP(char * commandp,int size)85*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun m525x_qspi_init();
90*4882a593Smuzhiyun m525x_i2c_init();
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /***************************************************************************/
94