1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m5249.c -- platform support for ColdFire 5249 based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /***************************************************************************/
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/param.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <asm/machdep.h>
18*4882a593Smuzhiyun #include <asm/coldfire.h>
19*4882a593Smuzhiyun #include <asm/mcfsim.h>
20*4882a593Smuzhiyun #include <asm/mcfclk.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /***************************************************************************/
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
25*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
26*4882a593Smuzhiyun DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
27*4882a593Smuzhiyun DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
28*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
29*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
30*4882a593Smuzhiyun DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
31*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
32*4882a593Smuzhiyun DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct clk *mcf_clks[] = {
35*4882a593Smuzhiyun &clk_pll,
36*4882a593Smuzhiyun &clk_sys,
37*4882a593Smuzhiyun &clk_mcftmr0,
38*4882a593Smuzhiyun &clk_mcftmr1,
39*4882a593Smuzhiyun &clk_mcfuart0,
40*4882a593Smuzhiyun &clk_mcfuart1,
41*4882a593Smuzhiyun &clk_mcfqspi0,
42*4882a593Smuzhiyun &clk_mcfi2c0,
43*4882a593Smuzhiyun &clk_mcfi2c1,
44*4882a593Smuzhiyun NULL
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /***************************************************************************/
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #ifdef CONFIG_M5249C3
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static struct resource m5249_smc91x_resources[] = {
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun .start = 0xe0000300,
54*4882a593Smuzhiyun .end = 0xe0000300 + 0x100,
55*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
56*4882a593Smuzhiyun },
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun .start = MCF_IRQ_GPIO6,
59*4882a593Smuzhiyun .end = MCF_IRQ_GPIO6,
60*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
61*4882a593Smuzhiyun },
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static struct platform_device m5249_smc91x = {
65*4882a593Smuzhiyun .name = "smc91x",
66*4882a593Smuzhiyun .id = 0,
67*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
68*4882a593Smuzhiyun .resource = m5249_smc91x_resources,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #endif /* CONFIG_M5249C3 */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static struct platform_device *m5249_devices[] __initdata = {
74*4882a593Smuzhiyun #ifdef CONFIG_M5249C3
75*4882a593Smuzhiyun &m5249_smc91x,
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /***************************************************************************/
80*4882a593Smuzhiyun
m5249_qspi_init(void)81*4882a593Smuzhiyun static void __init m5249_qspi_init(void)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
84*4882a593Smuzhiyun /* QSPI irq setup */
85*4882a593Smuzhiyun writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
86*4882a593Smuzhiyun MCFSIM_QSPIICR);
87*4882a593Smuzhiyun mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
88*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /***************************************************************************/
92*4882a593Smuzhiyun
m5249_i2c_init(void)93*4882a593Smuzhiyun static void __init m5249_i2c_init(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
96*4882a593Smuzhiyun u32 r;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* first I2C controller uses regular irq setup */
99*4882a593Smuzhiyun writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
100*4882a593Smuzhiyun MCFSIM_I2CICR);
101*4882a593Smuzhiyun mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* second I2C controller is completely different */
104*4882a593Smuzhiyun r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
105*4882a593Smuzhiyun r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
106*4882a593Smuzhiyun r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
107*4882a593Smuzhiyun writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
108*4882a593Smuzhiyun #endif /* CONFIG_I2C_IMX */
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /***************************************************************************/
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #ifdef CONFIG_M5249C3
114*4882a593Smuzhiyun
m5249_smc91x_init(void)115*4882a593Smuzhiyun static void __init m5249_smc91x_init(void)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun u32 gpio;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* Set the GPIO line as interrupt source for smc91x device */
120*4882a593Smuzhiyun gpio = readl(MCFSIM2_GPIOINTENABLE);
121*4882a593Smuzhiyun writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun gpio = readl(MCFINTC2_INTPRI5);
124*4882a593Smuzhiyun writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #endif /* CONFIG_M5249C3 */
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /***************************************************************************/
130*4882a593Smuzhiyun
config_BSP(char * commandp,int size)131*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #ifdef CONFIG_M5249C3
136*4882a593Smuzhiyun m5249_smc91x_init();
137*4882a593Smuzhiyun #endif
138*4882a593Smuzhiyun m5249_qspi_init();
139*4882a593Smuzhiyun m5249_i2c_init();
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /***************************************************************************/
143*4882a593Smuzhiyun
init_BSP(void)144*4882a593Smuzhiyun static int __init init_BSP(void)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun arch_initcall(init_BSP);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /***************************************************************************/
153