1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m523x.c -- platform support for ColdFire 523x based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Sub-architcture dependent initialization code for the Freescale
8*4882a593Smuzhiyun * 523x CPUs.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
11*4882a593Smuzhiyun * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /***************************************************************************/
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/param.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <asm/machdep.h>
21*4882a593Smuzhiyun #include <asm/coldfire.h>
22*4882a593Smuzhiyun #include <asm/mcfsim.h>
23*4882a593Smuzhiyun #include <asm/mcfclk.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /***************************************************************************/
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
28*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29*4882a593Smuzhiyun DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30*4882a593Smuzhiyun DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31*4882a593Smuzhiyun DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32*4882a593Smuzhiyun DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35*4882a593Smuzhiyun DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36*4882a593Smuzhiyun DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
37*4882a593Smuzhiyun DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct clk *mcf_clks[] = {
41*4882a593Smuzhiyun &clk_pll,
42*4882a593Smuzhiyun &clk_sys,
43*4882a593Smuzhiyun &clk_mcfpit0,
44*4882a593Smuzhiyun &clk_mcfpit1,
45*4882a593Smuzhiyun &clk_mcfpit2,
46*4882a593Smuzhiyun &clk_mcfpit3,
47*4882a593Smuzhiyun &clk_mcfuart0,
48*4882a593Smuzhiyun &clk_mcfuart1,
49*4882a593Smuzhiyun &clk_mcfuart2,
50*4882a593Smuzhiyun &clk_mcfqspi0,
51*4882a593Smuzhiyun &clk_fec0,
52*4882a593Smuzhiyun &clk_mcfi2c0,
53*4882a593Smuzhiyun NULL
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /***************************************************************************/
57*4882a593Smuzhiyun
m523x_qspi_init(void)58*4882a593Smuzhiyun static void __init m523x_qspi_init(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
61*4882a593Smuzhiyun u16 par;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* setup QSPS pins for QSPI with gpio CS control */
64*4882a593Smuzhiyun writeb(0x1f, MCFGPIO_PAR_QSPI);
65*4882a593Smuzhiyun /* and CS2 & CS3 as gpio */
66*4882a593Smuzhiyun par = readw(MCFGPIO_PAR_TIMER);
67*4882a593Smuzhiyun par &= 0x3f3f;
68*4882a593Smuzhiyun writew(par, MCFGPIO_PAR_TIMER);
69*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /***************************************************************************/
73*4882a593Smuzhiyun
m523x_i2c_init(void)74*4882a593Smuzhiyun static void __init m523x_i2c_init(void)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
77*4882a593Smuzhiyun u8 par;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* setup Port AS Pin Assignment Register for I2C */
80*4882a593Smuzhiyun /* set PASPA0 to SCL and PASPA1 to SDA */
81*4882a593Smuzhiyun par = readb(MCFGPIO_PAR_FECI2C);
82*4882a593Smuzhiyun par |= 0x0f;
83*4882a593Smuzhiyun writeb(par, MCFGPIO_PAR_FECI2C);
84*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /***************************************************************************/
88*4882a593Smuzhiyun
m523x_fec_init(void)89*4882a593Smuzhiyun static void __init m523x_fec_init(void)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun /* Set multi-function pins to ethernet use */
92*4882a593Smuzhiyun writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /***************************************************************************/
96*4882a593Smuzhiyun
config_BSP(char * commandp,int size)97*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
100*4882a593Smuzhiyun m523x_fec_init();
101*4882a593Smuzhiyun m523x_qspi_init();
102*4882a593Smuzhiyun m523x_i2c_init();
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /***************************************************************************/
106