1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * intc2.c -- support for the 2nd INTC controller of the 5249
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
7*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive
8*4882a593Smuzhiyun * for more details.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <asm/coldfire.h>
18*4882a593Smuzhiyun #include <asm/mcfsim.h>
19*4882a593Smuzhiyun
intc2_irq_gpio_mask(struct irq_data * d)20*4882a593Smuzhiyun static void intc2_irq_gpio_mask(struct irq_data *d)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun u32 imr;
23*4882a593Smuzhiyun imr = readl(MCFSIM2_GPIOINTENABLE);
24*4882a593Smuzhiyun imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
25*4882a593Smuzhiyun writel(imr, MCFSIM2_GPIOINTENABLE);
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
intc2_irq_gpio_unmask(struct irq_data * d)28*4882a593Smuzhiyun static void intc2_irq_gpio_unmask(struct irq_data *d)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun u32 imr;
31*4882a593Smuzhiyun imr = readl(MCFSIM2_GPIOINTENABLE);
32*4882a593Smuzhiyun imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
33*4882a593Smuzhiyun writel(imr, MCFSIM2_GPIOINTENABLE);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
intc2_irq_gpio_ack(struct irq_data * d)36*4882a593Smuzhiyun static void intc2_irq_gpio_ack(struct irq_data *d)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct irq_chip intc2_irq_gpio_chip = {
42*4882a593Smuzhiyun .name = "CF-INTC2",
43*4882a593Smuzhiyun .irq_mask = intc2_irq_gpio_mask,
44*4882a593Smuzhiyun .irq_unmask = intc2_irq_gpio_unmask,
45*4882a593Smuzhiyun .irq_ack = intc2_irq_gpio_ack,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
mcf_intc2_init(void)48*4882a593Smuzhiyun static int __init mcf_intc2_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun int irq;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* GPIO interrupt sources */
53*4882a593Smuzhiyun for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
54*4882a593Smuzhiyun irq_set_chip(irq, &intc2_irq_gpio_chip);
55*4882a593Smuzhiyun irq_set_handler(irq, handle_edge_irq);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun arch_initcall(mcf_intc2_init);
62