1*4882a593Smuzhiyun /***************************************************************************/
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun /*
4*4882a593Smuzhiyun * m68VZ328.c - 68VZ328 specific config
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 1993 Hamish Macdonald
7*4882a593Smuzhiyun * Copyright (C) 1999 D. Jeff Dionne
8*4882a593Smuzhiyun * Copyright (C) 2001 Georges Menie, Ken Desmet
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
11*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive
12*4882a593Smuzhiyun * for more details.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /***************************************************************************/
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun #include <linux/kernel.h>
20*4882a593Smuzhiyun #include <linux/kd.h>
21*4882a593Smuzhiyun #include <linux/netdevice.h>
22*4882a593Smuzhiyun #include <linux/interrupt.h>
23*4882a593Smuzhiyun #include <linux/irq.h>
24*4882a593Smuzhiyun #include <linux/rtc.h>
25*4882a593Smuzhiyun #include <linux/pgtable.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <asm/machdep.h>
28*4882a593Smuzhiyun #include <asm/MC68VZ328.h>
29*4882a593Smuzhiyun #include <asm/bootstd.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #ifdef CONFIG_INIT_LCD
32*4882a593Smuzhiyun #include "bootlogo-vz.h"
33*4882a593Smuzhiyun #endif
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /***************************************************************************/
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun int m68328_hwclk(int set, struct rtc_time *t);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /***************************************************************************/
40*4882a593Smuzhiyun /* Init Drangon Engine hardware */
41*4882a593Smuzhiyun /***************************************************************************/
42*4882a593Smuzhiyun #if defined(CONFIG_DRAGEN2)
43*4882a593Smuzhiyun
m68vz328_reset(void)44*4882a593Smuzhiyun static void m68vz328_reset(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun local_irq_disable();
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #ifdef CONFIG_INIT_LCD
49*4882a593Smuzhiyun PBDATA |= 0x20; /* disable CCFL light */
50*4882a593Smuzhiyun PKDATA |= 0x4; /* disable LCD controller */
51*4882a593Smuzhiyun LCKCON = 0;
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun __asm__ __volatile__(
55*4882a593Smuzhiyun "reset\n\t"
56*4882a593Smuzhiyun "moveal #0x04000000, %a0\n\t"
57*4882a593Smuzhiyun "moveal 0(%a0), %sp\n\t"
58*4882a593Smuzhiyun "moveal 4(%a0), %a0\n\t"
59*4882a593Smuzhiyun "jmp (%a0)"
60*4882a593Smuzhiyun );
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
init_hardware(char * command,int size)63*4882a593Smuzhiyun static void __init init_hardware(char *command, int size)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun #ifdef CONFIG_DIRECT_IO_ACCESS
66*4882a593Smuzhiyun SCR = 0x10; /* allow user access to internal registers */
67*4882a593Smuzhiyun #endif
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* CSGB Init */
70*4882a593Smuzhiyun CSGBB = 0x4000;
71*4882a593Smuzhiyun CSB = 0x1a1;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* CS8900 init */
74*4882a593Smuzhiyun /* PK3: hardware sleep function pin, active low */
75*4882a593Smuzhiyun PKSEL |= PK(3); /* select pin as I/O */
76*4882a593Smuzhiyun PKDIR |= PK(3); /* select pin as output */
77*4882a593Smuzhiyun PKDATA |= PK(3); /* set pin high */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* PF5: hardware reset function pin, active high */
80*4882a593Smuzhiyun PFSEL |= PF(5); /* select pin as I/O */
81*4882a593Smuzhiyun PFDIR |= PF(5); /* select pin as output */
82*4882a593Smuzhiyun PFDATA &= ~PF(5); /* set pin low */
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* cs8900 hardware reset */
85*4882a593Smuzhiyun PFDATA |= PF(5);
86*4882a593Smuzhiyun { int i; for (i = 0; i < 32000; ++i); }
87*4882a593Smuzhiyun PFDATA &= ~PF(5);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* INT1 enable (cs8900 IRQ) */
90*4882a593Smuzhiyun PDPOL &= ~PD(1); /* active high signal */
91*4882a593Smuzhiyun PDIQEG &= ~PD(1);
92*4882a593Smuzhiyun PDIRQEN |= PD(1); /* IRQ enabled */
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #ifdef CONFIG_INIT_LCD
95*4882a593Smuzhiyun /* initialize LCD controller */
96*4882a593Smuzhiyun LSSA = (long) screen_bits;
97*4882a593Smuzhiyun LVPW = 0x14;
98*4882a593Smuzhiyun LXMAX = 0x140;
99*4882a593Smuzhiyun LYMAX = 0xef;
100*4882a593Smuzhiyun LRRA = 0;
101*4882a593Smuzhiyun LPXCD = 3;
102*4882a593Smuzhiyun LPICF = 0x08;
103*4882a593Smuzhiyun LPOLCF = 0;
104*4882a593Smuzhiyun LCKCON = 0x80;
105*4882a593Smuzhiyun PCPDEN = 0xff;
106*4882a593Smuzhiyun PCSEL = 0;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Enable LCD controller */
109*4882a593Smuzhiyun PKDIR |= 0x4;
110*4882a593Smuzhiyun PKSEL |= 0x4;
111*4882a593Smuzhiyun PKDATA &= ~0x4;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Enable CCFL backlighting circuit */
114*4882a593Smuzhiyun PBDIR |= 0x20;
115*4882a593Smuzhiyun PBSEL |= 0x20;
116*4882a593Smuzhiyun PBDATA &= ~0x20;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* contrast control register */
119*4882a593Smuzhiyun PFDIR |= 0x1;
120*4882a593Smuzhiyun PFSEL &= ~0x1;
121*4882a593Smuzhiyun PWMR = 0x037F;
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /***************************************************************************/
126*4882a593Smuzhiyun /* Init RT-Control uCdimm hardware */
127*4882a593Smuzhiyun /***************************************************************************/
128*4882a593Smuzhiyun #elif defined(CONFIG_UCDIMM)
129*4882a593Smuzhiyun
m68vz328_reset(void)130*4882a593Smuzhiyun static void m68vz328_reset(void)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun local_irq_disable();
133*4882a593Smuzhiyun asm volatile (
134*4882a593Smuzhiyun "moveal #0x10c00000, %a0;\n\t"
135*4882a593Smuzhiyun "moveb #0, 0xFFFFF300;\n\t"
136*4882a593Smuzhiyun "moveal 0(%a0), %sp;\n\t"
137*4882a593Smuzhiyun "moveal 4(%a0), %a0;\n\t"
138*4882a593Smuzhiyun "jmp (%a0);\n"
139*4882a593Smuzhiyun );
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun unsigned char *cs8900a_hwaddr;
143*4882a593Smuzhiyun static int errno;
144*4882a593Smuzhiyun
_bsc0(char *,getserialnum)145*4882a593Smuzhiyun _bsc0(char *, getserialnum)
146*4882a593Smuzhiyun _bsc1(unsigned char *, gethwaddr, int, a)
147*4882a593Smuzhiyun _bsc1(char *, getbenv, char *, a)
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static void __init init_hardware(char *command, int size)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun char *p;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun pr_info("uCdimm serial string [%s]\n", getserialnum());
154*4882a593Smuzhiyun p = cs8900a_hwaddr = gethwaddr(0);
155*4882a593Smuzhiyun pr_info("uCdimm hwaddr %pM\n", p);
156*4882a593Smuzhiyun p = getbenv("APPEND");
157*4882a593Smuzhiyun if (p)
158*4882a593Smuzhiyun strcpy(p, command);
159*4882a593Smuzhiyun else
160*4882a593Smuzhiyun command[0] = 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /***************************************************************************/
164*4882a593Smuzhiyun #else
165*4882a593Smuzhiyun
m68vz328_reset(void)166*4882a593Smuzhiyun static void m68vz328_reset(void)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
init_hardware(char * command,int size)170*4882a593Smuzhiyun static void __init init_hardware(char *command, int size)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /***************************************************************************/
175*4882a593Smuzhiyun #endif
176*4882a593Smuzhiyun /***************************************************************************/
177*4882a593Smuzhiyun
config_BSP(char * command,int size)178*4882a593Smuzhiyun void __init config_BSP(char *command, int size)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun pr_info("68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n");
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun init_hardware(command, size);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
185*4882a593Smuzhiyun mach_hwclk = m68328_hwclk;
186*4882a593Smuzhiyun mach_reset = m68vz328_reset;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /***************************************************************************/
190