1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 1999-2000 Hewlett-Packard Co 4*4882a593Smuzhiyun * Copyright (C) 1999-2000 David Mosberger-Tang <davidm@hpl.hp.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 64-bit integer division. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This code is based on the application note entitled "Divide, Square Root 9*4882a593Smuzhiyun * and Remainder Algorithms for the IA-64 Architecture". This document 10*4882a593Smuzhiyun * is available as Intel document number 248725-002 or via the web at 11*4882a593Smuzhiyun * http://developer.intel.com/software/opensource/numerics/ 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * For more details on the theory behind these algorithms, see "IA-64 14*4882a593Smuzhiyun * and Elementary Functions" by Peter Markstein; HP Professional Books 15*4882a593Smuzhiyun * (http://www.goodreads.com/book/show/2019887.Ia_64_and_Elementary_Functions) 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun#include <asm/asmmacro.h> 19*4882a593Smuzhiyun#include <asm/export.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#ifdef MODULO 22*4882a593Smuzhiyun# define OP mod 23*4882a593Smuzhiyun#else 24*4882a593Smuzhiyun# define OP div 25*4882a593Smuzhiyun#endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun#ifdef UNSIGNED 28*4882a593Smuzhiyun# define SGN u 29*4882a593Smuzhiyun# define INT_TO_FP(a,b) fcvt.xuf.s1 a=b 30*4882a593Smuzhiyun# define FP_TO_INT(a,b) fcvt.fxu.trunc.s1 a=b 31*4882a593Smuzhiyun#else 32*4882a593Smuzhiyun# define SGN 33*4882a593Smuzhiyun# define INT_TO_FP(a,b) fcvt.xf a=b 34*4882a593Smuzhiyun# define FP_TO_INT(a,b) fcvt.fx.trunc.s1 a=b 35*4882a593Smuzhiyun#endif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun#define PASTE1(a,b) a##b 38*4882a593Smuzhiyun#define PASTE(a,b) PASTE1(a,b) 39*4882a593Smuzhiyun#define NAME PASTE(PASTE(__,SGN),PASTE(OP,di3)) 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunGLOBAL_ENTRY(NAME) 42*4882a593Smuzhiyun .regstk 2,0,0,0 43*4882a593Smuzhiyun // Transfer inputs to FP registers. 44*4882a593Smuzhiyun setf.sig f8 = in0 45*4882a593Smuzhiyun setf.sig f9 = in1 46*4882a593Smuzhiyun ;; 47*4882a593Smuzhiyun // Convert the inputs to FP, to avoid FP software-assist faults. 48*4882a593Smuzhiyun INT_TO_FP(f8, f8) 49*4882a593Smuzhiyun INT_TO_FP(f9, f9) 50*4882a593Smuzhiyun ;; 51*4882a593Smuzhiyun frcpa.s1 f11, p6 = f8, f9 // y0 = frcpa(b) 52*4882a593Smuzhiyun ;; 53*4882a593Smuzhiyun(p6) fmpy.s1 f7 = f8, f11 // q0 = a*y0 54*4882a593Smuzhiyun(p6) fnma.s1 f6 = f9, f11, f1 // e0 = -b*y0 + 1 55*4882a593Smuzhiyun ;; 56*4882a593Smuzhiyun(p6) fma.s1 f10 = f7, f6, f7 // q1 = q0*e0 + q0 57*4882a593Smuzhiyun(p6) fmpy.s1 f7 = f6, f6 // e1 = e0*e0 58*4882a593Smuzhiyun ;; 59*4882a593Smuzhiyun#ifdef MODULO 60*4882a593Smuzhiyun sub in1 = r0, in1 // in1 = -b 61*4882a593Smuzhiyun#endif 62*4882a593Smuzhiyun(p6) fma.s1 f10 = f10, f7, f10 // q2 = q1*e1 + q1 63*4882a593Smuzhiyun(p6) fma.s1 f6 = f11, f6, f11 // y1 = y0*e0 + y0 64*4882a593Smuzhiyun ;; 65*4882a593Smuzhiyun(p6) fma.s1 f6 = f6, f7, f6 // y2 = y1*e1 + y1 66*4882a593Smuzhiyun(p6) fnma.s1 f7 = f9, f10, f8 // r = -b*q2 + a 67*4882a593Smuzhiyun ;; 68*4882a593Smuzhiyun#ifdef MODULO 69*4882a593Smuzhiyun setf.sig f8 = in0 // f8 = a 70*4882a593Smuzhiyun setf.sig f9 = in1 // f9 = -b 71*4882a593Smuzhiyun#endif 72*4882a593Smuzhiyun(p6) fma.s1 f11 = f7, f6, f10 // q3 = r*y2 + q2 73*4882a593Smuzhiyun ;; 74*4882a593Smuzhiyun FP_TO_INT(f11, f11) // q = trunc(q3) 75*4882a593Smuzhiyun ;; 76*4882a593Smuzhiyun#ifdef MODULO 77*4882a593Smuzhiyun xma.l f11 = f11, f9, f8 // r = q*(-b) + a 78*4882a593Smuzhiyun ;; 79*4882a593Smuzhiyun#endif 80*4882a593Smuzhiyun getf.sig r8 = f11 // transfer result to result register 81*4882a593Smuzhiyun br.ret.sptk.many rp 82*4882a593SmuzhiyunEND(NAME) 83*4882a593SmuzhiyunEXPORT_SYMBOL(NAME) 84