1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2000 Hewlett-Packard Co 4*4882a593Smuzhiyun * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 32-bit integer division. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This code is based on the application note entitled "Divide, Square Root 9*4882a593Smuzhiyun * and Remainder Algorithms for the IA-64 Architecture". This document 10*4882a593Smuzhiyun * is available as Intel document number 248725-002 or via the web at 11*4882a593Smuzhiyun * http://developer.intel.com/software/opensource/numerics/ 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * For more details on the theory behind these algorithms, see "IA-64 14*4882a593Smuzhiyun * and Elementary Functions" by Peter Markstein; HP Professional Books 15*4882a593Smuzhiyun * (http://www.goodreads.com/book/show/2019887.Ia_64_and_Elementary_Functions) 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun#include <asm/asmmacro.h> 19*4882a593Smuzhiyun#include <asm/export.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#ifdef MODULO 22*4882a593Smuzhiyun# define OP mod 23*4882a593Smuzhiyun#else 24*4882a593Smuzhiyun# define OP div 25*4882a593Smuzhiyun#endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun#ifdef UNSIGNED 28*4882a593Smuzhiyun# define SGN u 29*4882a593Smuzhiyun# define EXTEND zxt4 30*4882a593Smuzhiyun# define INT_TO_FP(a,b) fcvt.xuf.s1 a=b 31*4882a593Smuzhiyun# define FP_TO_INT(a,b) fcvt.fxu.trunc.s1 a=b 32*4882a593Smuzhiyun#else 33*4882a593Smuzhiyun# define SGN 34*4882a593Smuzhiyun# define EXTEND sxt4 35*4882a593Smuzhiyun# define INT_TO_FP(a,b) fcvt.xf a=b 36*4882a593Smuzhiyun# define FP_TO_INT(a,b) fcvt.fx.trunc.s1 a=b 37*4882a593Smuzhiyun#endif 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun#define PASTE1(a,b) a##b 40*4882a593Smuzhiyun#define PASTE(a,b) PASTE1(a,b) 41*4882a593Smuzhiyun#define NAME PASTE(PASTE(__,SGN),PASTE(OP,si3)) 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunGLOBAL_ENTRY(NAME) 44*4882a593Smuzhiyun .regstk 2,0,0,0 45*4882a593Smuzhiyun // Transfer inputs to FP registers. 46*4882a593Smuzhiyun mov r2 = 0xffdd // r2 = -34 + 65535 (fp reg format bias) 47*4882a593Smuzhiyun EXTEND in0 = in0 // in0 = a 48*4882a593Smuzhiyun EXTEND in1 = in1 // in1 = b 49*4882a593Smuzhiyun ;; 50*4882a593Smuzhiyun setf.sig f8 = in0 51*4882a593Smuzhiyun setf.sig f9 = in1 52*4882a593Smuzhiyun#ifdef MODULO 53*4882a593Smuzhiyun sub in1 = r0, in1 // in1 = -b 54*4882a593Smuzhiyun#endif 55*4882a593Smuzhiyun ;; 56*4882a593Smuzhiyun // Convert the inputs to FP, to avoid FP software-assist faults. 57*4882a593Smuzhiyun INT_TO_FP(f8, f8) 58*4882a593Smuzhiyun INT_TO_FP(f9, f9) 59*4882a593Smuzhiyun ;; 60*4882a593Smuzhiyun setf.exp f7 = r2 // f7 = 2^-34 61*4882a593Smuzhiyun frcpa.s1 f6, p6 = f8, f9 // y0 = frcpa(b) 62*4882a593Smuzhiyun ;; 63*4882a593Smuzhiyun(p6) fmpy.s1 f8 = f8, f6 // q0 = a*y0 64*4882a593Smuzhiyun(p6) fnma.s1 f6 = f9, f6, f1 // e0 = -b*y0 + 1 65*4882a593Smuzhiyun ;; 66*4882a593Smuzhiyun#ifdef MODULO 67*4882a593Smuzhiyun setf.sig f9 = in1 // f9 = -b 68*4882a593Smuzhiyun#endif 69*4882a593Smuzhiyun(p6) fma.s1 f8 = f6, f8, f8 // q1 = e0*q0 + q0 70*4882a593Smuzhiyun(p6) fma.s1 f6 = f6, f6, f7 // e1 = e0*e0 + 2^-34 71*4882a593Smuzhiyun ;; 72*4882a593Smuzhiyun#ifdef MODULO 73*4882a593Smuzhiyun setf.sig f7 = in0 74*4882a593Smuzhiyun#endif 75*4882a593Smuzhiyun(p6) fma.s1 f6 = f6, f8, f8 // q2 = e1*q1 + q1 76*4882a593Smuzhiyun ;; 77*4882a593Smuzhiyun FP_TO_INT(f6, f6) // q = trunc(q2) 78*4882a593Smuzhiyun ;; 79*4882a593Smuzhiyun#ifdef MODULO 80*4882a593Smuzhiyun xma.l f6 = f6, f9, f7 // r = q*(-b) + a 81*4882a593Smuzhiyun ;; 82*4882a593Smuzhiyun#endif 83*4882a593Smuzhiyun getf.sig r8 = f6 // transfer result to result register 84*4882a593Smuzhiyun br.ret.sptk.many rp 85*4882a593SmuzhiyunEND(NAME) 86*4882a593SmuzhiyunEXPORT_SYMBOL(NAME) 87