1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_IA64_XTP_H 3*4882a593Smuzhiyun #define _ASM_IA64_XTP_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/io.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifdef CONFIG_SMP 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define XTP_OFFSET 0x1e0008 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SMP_IRQ_REDIRECTION (1 << 0) 12*4882a593Smuzhiyun #define SMP_IPI_REDIRECTION (1 << 1) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun extern unsigned char smp_int_redirect; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * XTP control functions: 18*4882a593Smuzhiyun * min_xtp : route all interrupts to this CPU 19*4882a593Smuzhiyun * normal_xtp: nominal XTP value 20*4882a593Smuzhiyun * max_xtp : never deliver interrupts to this CPU. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun static inline void min_xtp(void)24*4882a593Smuzhiyunmin_xtp (void) 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun if (smp_int_redirect & SMP_IRQ_REDIRECTION) 27*4882a593Smuzhiyun writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */ 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun static inline void normal_xtp(void)31*4882a593Smuzhiyunnormal_xtp (void) 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun if (smp_int_redirect & SMP_IRQ_REDIRECTION) 34*4882a593Smuzhiyun writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */ 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun static inline void max_xtp(void)38*4882a593Smuzhiyunmax_xtp (void) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun if (smp_int_redirect & SMP_IRQ_REDIRECTION) 41*4882a593Smuzhiyun writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */ 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* CONFIG_SMP */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* _ASM_IA64_XTP_Hy */ 47