1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ASM_IA64_TLBFLUSH_H
3*4882a593Smuzhiyun #define _ASM_IA64_TLBFLUSH_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /*
6*4882a593Smuzhiyun * Copyright (C) 2002 Hewlett-Packard Co
7*4882a593Smuzhiyun * David Mosberger-Tang <davidm@hpl.hp.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/mm.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/intrinsics.h>
14*4882a593Smuzhiyun #include <asm/mmu_context.h>
15*4882a593Smuzhiyun #include <asm/page.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct ia64_tr_entry {
18*4882a593Smuzhiyun u64 ifa;
19*4882a593Smuzhiyun u64 itir;
20*4882a593Smuzhiyun u64 pte;
21*4882a593Smuzhiyun u64 rr;
22*4882a593Smuzhiyun }; /*Record for tr entry!*/
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
25*4882a593Smuzhiyun extern void ia64_ptr_entry(u64 target_mask, int slot);
26*4882a593Smuzhiyun extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun region register macros
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001)
32*4882a593Smuzhiyun #define RR_VE(val) (((val) & 0x0000000000000001) << 0)
33*4882a593Smuzhiyun #define RR_VE_MASK 0x0000000000000001L
34*4882a593Smuzhiyun #define RR_VE_SHIFT 0
35*4882a593Smuzhiyun #define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f)
36*4882a593Smuzhiyun #define RR_PS(val) (((val) & 0x000000000000003f) << 2)
37*4882a593Smuzhiyun #define RR_PS_MASK 0x00000000000000fcL
38*4882a593Smuzhiyun #define RR_PS_SHIFT 2
39*4882a593Smuzhiyun #define RR_RID_MASK 0x00000000ffffff00L
40*4882a593Smuzhiyun #define RR_TO_RID(val) ((val >> 8) & 0xffffff)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * Now for some TLB flushing routines. This is the kind of stuff that
44*4882a593Smuzhiyun * can be very expensive, so try to avoid them whenever possible.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun extern void setup_ptcg_sem(int max_purges, int from_palo);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Flush everything (kernel mapping may also have changed due to
50*4882a593Smuzhiyun * vmalloc/vfree).
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun extern void local_flush_tlb_all (void);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #ifdef CONFIG_SMP
55*4882a593Smuzhiyun extern void smp_flush_tlb_all (void);
56*4882a593Smuzhiyun extern void smp_flush_tlb_mm (struct mm_struct *mm);
57*4882a593Smuzhiyun extern void smp_flush_tlb_cpumask (cpumask_t xcpumask);
58*4882a593Smuzhiyun # define flush_tlb_all() smp_flush_tlb_all()
59*4882a593Smuzhiyun #else
60*4882a593Smuzhiyun # define flush_tlb_all() local_flush_tlb_all()
61*4882a593Smuzhiyun # define smp_flush_tlb_cpumask(m) local_flush_tlb_all()
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static inline void
local_finish_flush_tlb_mm(struct mm_struct * mm)65*4882a593Smuzhiyun local_finish_flush_tlb_mm (struct mm_struct *mm)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun if (mm == current->active_mm)
68*4882a593Smuzhiyun activate_context(mm);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * Flush a specified user mapping. This is called, e.g., as a result of fork() and
73*4882a593Smuzhiyun * exit(). fork() ends up here because the copy-on-write mechanism needs to write-protect
74*4882a593Smuzhiyun * the PTEs of the parent task.
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun static inline void
flush_tlb_mm(struct mm_struct * mm)77*4882a593Smuzhiyun flush_tlb_mm (struct mm_struct *mm)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun if (!mm)
80*4882a593Smuzhiyun return;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun set_bit(mm->context, ia64_ctx.flushmap);
83*4882a593Smuzhiyun mm->context = 0;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (atomic_read(&mm->mm_users) == 0)
86*4882a593Smuzhiyun return; /* happens as a result of exit_mmap() */
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #ifdef CONFIG_SMP
89*4882a593Smuzhiyun smp_flush_tlb_mm(mm);
90*4882a593Smuzhiyun #else
91*4882a593Smuzhiyun local_finish_flush_tlb_mm(mm);
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * Page-granular tlb flush.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun static inline void
flush_tlb_page(struct vm_area_struct * vma,unsigned long addr)101*4882a593Smuzhiyun flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun #ifdef CONFIG_SMP
104*4882a593Smuzhiyun flush_tlb_range(vma, (addr & PAGE_MASK), (addr & PAGE_MASK) + PAGE_SIZE);
105*4882a593Smuzhiyun #else
106*4882a593Smuzhiyun if (vma->vm_mm == current->active_mm)
107*4882a593Smuzhiyun ia64_ptcl(addr, (PAGE_SHIFT << 2));
108*4882a593Smuzhiyun else
109*4882a593Smuzhiyun vma->vm_mm->context = 0;
110*4882a593Smuzhiyun #endif
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun * Flush the local TLB. Invoked from another cpu using an IPI.
115*4882a593Smuzhiyun */
116*4882a593Smuzhiyun #ifdef CONFIG_SMP
117*4882a593Smuzhiyun void smp_local_flush_tlb(void);
118*4882a593Smuzhiyun #else
119*4882a593Smuzhiyun #define smp_local_flush_tlb()
120*4882a593Smuzhiyun #endif
121*4882a593Smuzhiyun
flush_tlb_kernel_range(unsigned long start,unsigned long end)122*4882a593Smuzhiyun static inline void flush_tlb_kernel_range(unsigned long start,
123*4882a593Smuzhiyun unsigned long end)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun flush_tlb_all(); /* XXX fix me */
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #endif /* _ASM_IA64_TLBFLUSH_H */
129