1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /****************************************************************************** 3*4882a593Smuzhiyun * arch/ia64/include/asm/native/inst.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> 6*4882a593Smuzhiyun * VA Linux Systems Japan K.K. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define DO_SAVE_MIN IA64_NATIVE_DO_SAVE_MIN 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MOV_FROM_IFA(reg) \ 12*4882a593Smuzhiyun mov reg = cr.ifa 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MOV_FROM_ITIR(reg) \ 15*4882a593Smuzhiyun mov reg = cr.itir 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MOV_FROM_ISR(reg) \ 18*4882a593Smuzhiyun mov reg = cr.isr 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MOV_FROM_IHA(reg) \ 21*4882a593Smuzhiyun mov reg = cr.iha 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MOV_FROM_IPSR(pred, reg) \ 24*4882a593Smuzhiyun (pred) mov reg = cr.ipsr 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MOV_FROM_IIM(reg) \ 27*4882a593Smuzhiyun mov reg = cr.iim 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define MOV_FROM_IIP(reg) \ 30*4882a593Smuzhiyun mov reg = cr.iip 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MOV_FROM_IVR(reg, clob) \ 33*4882a593Smuzhiyun mov reg = cr.ivr 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MOV_FROM_PSR(pred, reg, clob) \ 36*4882a593Smuzhiyun (pred) mov reg = psr 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MOV_FROM_ITC(pred, pred_clob, reg, clob) \ 39*4882a593Smuzhiyun (pred) mov reg = ar.itc 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MOV_TO_IFA(reg, clob) \ 42*4882a593Smuzhiyun mov cr.ifa = reg 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MOV_TO_ITIR(pred, reg, clob) \ 45*4882a593Smuzhiyun (pred) mov cr.itir = reg 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MOV_TO_IHA(pred, reg, clob) \ 48*4882a593Smuzhiyun (pred) mov cr.iha = reg 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define MOV_TO_IPSR(pred, reg, clob) \ 51*4882a593Smuzhiyun (pred) mov cr.ipsr = reg 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MOV_TO_IFS(pred, reg, clob) \ 54*4882a593Smuzhiyun (pred) mov cr.ifs = reg 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MOV_TO_IIP(reg, clob) \ 57*4882a593Smuzhiyun mov cr.iip = reg 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MOV_TO_KR(kr, reg, clob0, clob1) \ 60*4882a593Smuzhiyun mov IA64_KR(kr) = reg 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define ITC_I(pred, reg, clob) \ 63*4882a593Smuzhiyun (pred) itc.i reg 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define ITC_D(pred, reg, clob) \ 66*4882a593Smuzhiyun (pred) itc.d reg 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define ITC_I_AND_D(pred_i, pred_d, reg, clob) \ 69*4882a593Smuzhiyun (pred_i) itc.i reg; \ 70*4882a593Smuzhiyun (pred_d) itc.d reg 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define THASH(pred, reg0, reg1, clob) \ 73*4882a593Smuzhiyun (pred) thash reg0 = reg1 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \ 76*4882a593Smuzhiyun ssm psr.ic | PSR_DEFAULT_BITS \ 77*4882a593Smuzhiyun ;; \ 78*4882a593Smuzhiyun srlz.i /* guarantee that interruption collectin is on */ \ 79*4882a593Smuzhiyun ;; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \ 82*4882a593Smuzhiyun ssm psr.ic \ 83*4882a593Smuzhiyun ;; \ 84*4882a593Smuzhiyun srlz.d 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define RSM_PSR_IC(clob) \ 87*4882a593Smuzhiyun rsm psr.ic 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define SSM_PSR_I(pred, pred_clob, clob) \ 90*4882a593Smuzhiyun (pred) ssm psr.i 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define RSM_PSR_I(pred, clob0, clob1) \ 93*4882a593Smuzhiyun (pred) rsm psr.i 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define RSM_PSR_I_IC(clob0, clob1, clob2) \ 96*4882a593Smuzhiyun rsm psr.i | psr.ic 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define RSM_PSR_DT \ 99*4882a593Smuzhiyun rsm psr.dt 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define RSM_PSR_BE_I(clob0, clob1) \ 102*4882a593Smuzhiyun rsm psr.be | psr.i 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define SSM_PSR_DT_AND_SRLZ_I \ 105*4882a593Smuzhiyun ssm psr.dt \ 106*4882a593Smuzhiyun ;; \ 107*4882a593Smuzhiyun srlz.i 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define BSW_0(clob0, clob1, clob2) \ 110*4882a593Smuzhiyun bsw.0 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define BSW_1(clob0, clob1) \ 113*4882a593Smuzhiyun bsw.1 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define COVER \ 116*4882a593Smuzhiyun cover 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define RFI \ 119*4882a593Smuzhiyun rfi 120