1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ASM_IA64_IOSAPIC_H
3*4882a593Smuzhiyun #define __ASM_IA64_IOSAPIC_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #define IOSAPIC_REG_SELECT 0x0
6*4882a593Smuzhiyun #define IOSAPIC_WINDOW 0x10
7*4882a593Smuzhiyun #define IOSAPIC_EOI 0x40
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define IOSAPIC_VERSION 0x1
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun * Redirection table entry
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun #define IOSAPIC_RTE_LOW(i) (0x10+i*2)
15*4882a593Smuzhiyun #define IOSAPIC_RTE_HIGH(i) (0x11+i*2)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define IOSAPIC_DEST_SHIFT 16
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Delivery mode
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #define IOSAPIC_DELIVERY_SHIFT 8
23*4882a593Smuzhiyun #define IOSAPIC_FIXED 0x0
24*4882a593Smuzhiyun #define IOSAPIC_LOWEST_PRIORITY 0x1
25*4882a593Smuzhiyun #define IOSAPIC_PMI 0x2
26*4882a593Smuzhiyun #define IOSAPIC_NMI 0x4
27*4882a593Smuzhiyun #define IOSAPIC_INIT 0x5
28*4882a593Smuzhiyun #define IOSAPIC_EXTINT 0x7
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Interrupt polarity
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun #define IOSAPIC_POLARITY_SHIFT 13
34*4882a593Smuzhiyun #define IOSAPIC_POL_HIGH 0
35*4882a593Smuzhiyun #define IOSAPIC_POL_LOW 1
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Trigger mode
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun #define IOSAPIC_TRIGGER_SHIFT 15
41*4882a593Smuzhiyun #define IOSAPIC_EDGE 0
42*4882a593Smuzhiyun #define IOSAPIC_LEVEL 1
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Mask bit
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define IOSAPIC_MASK_SHIFT 16
49*4882a593Smuzhiyun #define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define IOSAPIC_VECTOR_MASK 0xffffff00
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #ifndef __ASSEMBLY__
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define NR_IOSAPICS 256
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init
58*4882a593Smuzhiyun #define __iosapic_read __ia64_native_iosapic_read
59*4882a593Smuzhiyun #define __iosapic_write __ia64_native_iosapic_write
60*4882a593Smuzhiyun #define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun extern void __init ia64_native_iosapic_pcat_compat_init(void);
63*4882a593Smuzhiyun extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static inline unsigned int
__ia64_native_iosapic_read(char __iomem * iosapic,unsigned int reg)66*4882a593Smuzhiyun __ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun writel(reg, iosapic + IOSAPIC_REG_SELECT);
69*4882a593Smuzhiyun return readl(iosapic + IOSAPIC_WINDOW);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static inline void
__ia64_native_iosapic_write(char __iomem * iosapic,unsigned int reg,u32 val)73*4882a593Smuzhiyun __ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun writel(reg, iosapic + IOSAPIC_REG_SELECT);
76*4882a593Smuzhiyun writel(val, iosapic + IOSAPIC_WINDOW);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
iosapic_eoi(char __iomem * iosapic,u32 vector)79*4882a593Smuzhiyun static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun writel(vector, iosapic + IOSAPIC_EOI);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun extern void __init iosapic_system_init (int pcat_compat);
85*4882a593Smuzhiyun extern int iosapic_init (unsigned long address, unsigned int gsi_base);
86*4882a593Smuzhiyun extern int iosapic_remove (unsigned int gsi_base);
87*4882a593Smuzhiyun extern int gsi_to_irq (unsigned int gsi);
88*4882a593Smuzhiyun extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
89*4882a593Smuzhiyun unsigned long trigger);
90*4882a593Smuzhiyun extern void iosapic_unregister_intr (unsigned int irq);
91*4882a593Smuzhiyun extern void iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
92*4882a593Smuzhiyun unsigned long polarity,
93*4882a593Smuzhiyun unsigned long trigger);
94*4882a593Smuzhiyun extern int __init iosapic_register_platform_intr (u32 int_type,
95*4882a593Smuzhiyun unsigned int gsi,
96*4882a593Smuzhiyun int pmi_vector,
97*4882a593Smuzhiyun u16 eid, u16 id,
98*4882a593Smuzhiyun unsigned long polarity,
99*4882a593Smuzhiyun unsigned long trigger);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #ifdef CONFIG_NUMA
102*4882a593Smuzhiyun extern void map_iosapic_to_node (unsigned int, int);
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun # endif /* !__ASSEMBLY__ */
106*4882a593Smuzhiyun #endif /* __ASM_IA64_IOSAPIC_H */
107