1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Hexagon VM page table entry definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2010-2011,2013 The Linux Foundation. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_VM_MMU_H 9*4882a593Smuzhiyun #define _ASM_VM_MMU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Shift, mask, and other constants for the Hexagon Virtual Machine 13*4882a593Smuzhiyun * page tables. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Virtual machine MMU allows first-level entries to either be 16*4882a593Smuzhiyun * single-level lookup PTEs for very large pages, or PDEs pointing 17*4882a593Smuzhiyun * to second-level PTEs for smaller pages. If PTE is single-level, 18*4882a593Smuzhiyun * the least significant bits cannot be used as software bits to encode 19*4882a593Smuzhiyun * virtual memory subsystem information about the page, and that state 20*4882a593Smuzhiyun * must be maintained in some parallel data structure. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* S or Page Size field in PDE */ 24*4882a593Smuzhiyun #define __HVM_PDE_S (0x7 << 0) 25*4882a593Smuzhiyun #define __HVM_PDE_S_4KB 0 26*4882a593Smuzhiyun #define __HVM_PDE_S_16KB 1 27*4882a593Smuzhiyun #define __HVM_PDE_S_64KB 2 28*4882a593Smuzhiyun #define __HVM_PDE_S_256KB 3 29*4882a593Smuzhiyun #define __HVM_PDE_S_1MB 4 30*4882a593Smuzhiyun #define __HVM_PDE_S_4MB 5 31*4882a593Smuzhiyun #define __HVM_PDE_S_16MB 6 32*4882a593Smuzhiyun #define __HVM_PDE_S_INVALID 7 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Masks for L2 page table pointer, as function of page size */ 35*4882a593Smuzhiyun #define __HVM_PDE_PTMASK_4KB 0xfffff000 36*4882a593Smuzhiyun #define __HVM_PDE_PTMASK_16KB 0xfffffc00 37*4882a593Smuzhiyun #define __HVM_PDE_PTMASK_64KB 0xffffff00 38*4882a593Smuzhiyun #define __HVM_PDE_PTMASK_256KB 0xffffffc0 39*4882a593Smuzhiyun #define __HVM_PDE_PTMASK_1MB 0xfffffff0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Virtual Machine PTE Bits/Fields 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define __HVM_PTE_T (1<<4) 45*4882a593Smuzhiyun #define __HVM_PTE_U (1<<5) 46*4882a593Smuzhiyun #define __HVM_PTE_C (0x7<<6) 47*4882a593Smuzhiyun #define __HVM_PTE_CVAL(pte) (((pte) & __HVM_PTE_C) >> 6) 48*4882a593Smuzhiyun #define __HVM_PTE_R (1<<9) 49*4882a593Smuzhiyun #define __HVM_PTE_W (1<<10) 50*4882a593Smuzhiyun #define __HVM_PTE_X (1<<11) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Cache Attributes, to be shifted as necessary for virtual/physical PTEs 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define __HEXAGON_C_WB 0x0 /* Write-back, no L2 */ 57*4882a593Smuzhiyun #define __HEXAGON_C_WT 0x1 /* Write-through, no L2 */ 58*4882a593Smuzhiyun #define __HEXAGON_C_UNC 0x6 /* Uncached memory */ 59*4882a593Smuzhiyun #if CONFIG_HEXAGON_ARCH_VERSION >= 2 60*4882a593Smuzhiyun #define __HEXAGON_C_DEV 0x4 /* Device register space */ 61*4882a593Smuzhiyun #else 62*4882a593Smuzhiyun #define __HEXAGON_C_DEV __HEXAGON_C_UNC 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun #define __HEXAGON_C_WT_L2 0x5 /* Write-through, with L2 */ 65*4882a593Smuzhiyun #define __HEXAGON_C_WB_L2 0x7 /* Write-back, with L2 */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * This can be overridden, but we're defaulting to the most aggressive 69*4882a593Smuzhiyun * cache policy, the better to find bugs sooner. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define CACHE_DEFAULT __HEXAGON_C_WB_L2 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Masks for physical page address, as a function of page size */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_4KB 0xfffff000 77*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_16KB 0xffffc000 78*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_64KB 0xffff0000 79*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_256KB 0xfffc0000 80*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_1MB 0xfff00000 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Masks for single-level large page lookups */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_4MB 0xffc00000 85*4882a593Smuzhiyun #define __HVM_PTE_PGMASK_16MB 0xff000000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * "Big kernel page mappings" (see vm_init_segtable.S) 89*4882a593Smuzhiyun * are currently 16MB 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define BIG_KERNEL_PAGE_SHIFT 24 93*4882a593Smuzhiyun #define BIG_KERNEL_PAGE_SIZE (1 << BIG_KERNEL_PAGE_SHIFT) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* _ASM_VM_MMU_H */ 98