1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * IO definitions for the Hexagon architecture
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _ASM_IO_H
9*4882a593Smuzhiyun #define _ASM_IO_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifdef __KERNEL__
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/types.h>
14*4882a593Smuzhiyun #include <asm/iomap.h>
15*4882a593Smuzhiyun #include <asm/page.h>
16*4882a593Smuzhiyun #include <asm/cacheflush.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * We don't have PCI yet.
20*4882a593Smuzhiyun * _IO_BASE is pointing at what should be unused virtual space.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #define IO_SPACE_LIMIT 0xffff
23*4882a593Smuzhiyun #define _IO_BASE ((void __iomem *)0xfe000000)
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define IOMEM(x) ((void __force __iomem *)(x))
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
28*4882a593Smuzhiyun unsigned long end, unsigned long flags);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun extern void iounmap(const volatile void __iomem *addr);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Defined in lib/io.c, needed for smc91x driver. */
33*4882a593Smuzhiyun extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
34*4882a593Smuzhiyun extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
37*4882a593Smuzhiyun extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define readsw(p, d, l) __raw_readsw(p, d, l)
40*4882a593Smuzhiyun #define writesw(p, d, l) __raw_writesw(p, d, l)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define readsl(p, d, l) __raw_readsl(p, d, l)
43*4882a593Smuzhiyun #define writesl(p, d, l) __raw_writesl(p, d, l)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * virt_to_phys - map virtual address to physical
47*4882a593Smuzhiyun * @address: address to map
48*4882a593Smuzhiyun */
virt_to_phys(volatile void * address)49*4882a593Smuzhiyun static inline unsigned long virt_to_phys(volatile void *address)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun return __pa(address);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * phys_to_virt - map physical address to virtual
56*4882a593Smuzhiyun * @address: address to map
57*4882a593Smuzhiyun */
phys_to_virt(unsigned long address)58*4882a593Smuzhiyun static inline void *phys_to_virt(unsigned long address)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun return __va(address);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * convert a physical pointer to a virtual kernel pointer for
65*4882a593Smuzhiyun * /dev/mem access.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun #define xlate_dev_kmem_ptr(p) __va(p)
68*4882a593Smuzhiyun #define xlate_dev_mem_ptr(p) __va(p)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * IO port access primitives. Hexagon doesn't have special IO access
72*4882a593Smuzhiyun * instructions; all I/O is memory mapped.
73*4882a593Smuzhiyun *
74*4882a593Smuzhiyun * in/out are used for "ports", but we don't have "port instructions",
75*4882a593Smuzhiyun * so these are really just memory mapped too.
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * readb - read byte from memory mapped device
80*4882a593Smuzhiyun * @addr: pointer to memory
81*4882a593Smuzhiyun *
82*4882a593Smuzhiyun * Operates on "I/O bus memory space"
83*4882a593Smuzhiyun */
readb(const volatile void __iomem * addr)84*4882a593Smuzhiyun static inline u8 readb(const volatile void __iomem *addr)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun u8 val;
87*4882a593Smuzhiyun asm volatile(
88*4882a593Smuzhiyun "%0 = memb(%1);"
89*4882a593Smuzhiyun : "=&r" (val)
90*4882a593Smuzhiyun : "r" (addr)
91*4882a593Smuzhiyun );
92*4882a593Smuzhiyun return val;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
readw(const volatile void __iomem * addr)95*4882a593Smuzhiyun static inline u16 readw(const volatile void __iomem *addr)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun u16 val;
98*4882a593Smuzhiyun asm volatile(
99*4882a593Smuzhiyun "%0 = memh(%1);"
100*4882a593Smuzhiyun : "=&r" (val)
101*4882a593Smuzhiyun : "r" (addr)
102*4882a593Smuzhiyun );
103*4882a593Smuzhiyun return val;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
readl(const volatile void __iomem * addr)106*4882a593Smuzhiyun static inline u32 readl(const volatile void __iomem *addr)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun u32 val;
109*4882a593Smuzhiyun asm volatile(
110*4882a593Smuzhiyun "%0 = memw(%1);"
111*4882a593Smuzhiyun : "=&r" (val)
112*4882a593Smuzhiyun : "r" (addr)
113*4882a593Smuzhiyun );
114*4882a593Smuzhiyun return val;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * writeb - write a byte to a memory location
119*4882a593Smuzhiyun * @data: data to write to
120*4882a593Smuzhiyun * @addr: pointer to memory
121*4882a593Smuzhiyun *
122*4882a593Smuzhiyun */
writeb(u8 data,volatile void __iomem * addr)123*4882a593Smuzhiyun static inline void writeb(u8 data, volatile void __iomem *addr)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun asm volatile(
126*4882a593Smuzhiyun "memb(%0) = %1;"
127*4882a593Smuzhiyun :
128*4882a593Smuzhiyun : "r" (addr), "r" (data)
129*4882a593Smuzhiyun : "memory"
130*4882a593Smuzhiyun );
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
writew(u16 data,volatile void __iomem * addr)133*4882a593Smuzhiyun static inline void writew(u16 data, volatile void __iomem *addr)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun asm volatile(
136*4882a593Smuzhiyun "memh(%0) = %1;"
137*4882a593Smuzhiyun :
138*4882a593Smuzhiyun : "r" (addr), "r" (data)
139*4882a593Smuzhiyun : "memory"
140*4882a593Smuzhiyun );
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
writel(u32 data,volatile void __iomem * addr)144*4882a593Smuzhiyun static inline void writel(u32 data, volatile void __iomem *addr)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun asm volatile(
147*4882a593Smuzhiyun "memw(%0) = %1;"
148*4882a593Smuzhiyun :
149*4882a593Smuzhiyun : "r" (addr), "r" (data)
150*4882a593Smuzhiyun : "memory"
151*4882a593Smuzhiyun );
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun #define __raw_writeb writeb
155*4882a593Smuzhiyun #define __raw_writew writew
156*4882a593Smuzhiyun #define __raw_writel writel
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define __raw_readb readb
159*4882a593Smuzhiyun #define __raw_readw readw
160*4882a593Smuzhiyun #define __raw_readl readl
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
164*4882a593Smuzhiyun */
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun #define readb_relaxed __raw_readb
167*4882a593Smuzhiyun #define readw_relaxed __raw_readw
168*4882a593Smuzhiyun #define readl_relaxed __raw_readl
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun #define writeb_relaxed __raw_writeb
171*4882a593Smuzhiyun #define writew_relaxed __raw_writew
172*4882a593Smuzhiyun #define writel_relaxed __raw_writel
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun void __iomem *ioremap(unsigned long phys_addr, unsigned long size);
175*4882a593Smuzhiyun #define ioremap_uc(X, Y) ioremap((X), (Y))
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun #define __raw_writel writel
179*4882a593Smuzhiyun
memcpy_fromio(void * dst,const volatile void __iomem * src,int count)180*4882a593Smuzhiyun static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
181*4882a593Smuzhiyun int count)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun memcpy(dst, (void *) src, count);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
memcpy_toio(volatile void __iomem * dst,const void * src,int count)186*4882a593Smuzhiyun static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
187*4882a593Smuzhiyun int count)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun memcpy((void *) dst, src, count);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
memset_io(volatile void __iomem * addr,int value,size_t size)192*4882a593Smuzhiyun static inline void memset_io(volatile void __iomem *addr, int value,
193*4882a593Smuzhiyun size_t size)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun memset((void __force *)addr, value, size);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun #define PCI_IO_ADDR (volatile void __iomem *)
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /*
201*4882a593Smuzhiyun * inb - read byte from I/O port or something
202*4882a593Smuzhiyun * @port: address in I/O space
203*4882a593Smuzhiyun *
204*4882a593Smuzhiyun * Operates on "I/O bus I/O space"
205*4882a593Smuzhiyun */
inb(unsigned long port)206*4882a593Smuzhiyun static inline u8 inb(unsigned long port)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
inw(unsigned long port)211*4882a593Smuzhiyun static inline u16 inw(unsigned long port)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
inl(unsigned long port)216*4882a593Smuzhiyun static inline u32 inl(unsigned long port)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun /*
222*4882a593Smuzhiyun * outb - write a byte to a memory location
223*4882a593Smuzhiyun * @data: data to write to
224*4882a593Smuzhiyun * @addr: address in I/O space
225*4882a593Smuzhiyun */
outb(u8 data,unsigned long port)226*4882a593Smuzhiyun static inline void outb(u8 data, unsigned long port)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
outw(u16 data,unsigned long port)231*4882a593Smuzhiyun static inline void outw(u16 data, unsigned long port)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
outl(u32 data,unsigned long port)236*4882a593Smuzhiyun static inline void outl(u32 data, unsigned long port)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun #define outb_p outb
242*4882a593Smuzhiyun #define outw_p outw
243*4882a593Smuzhiyun #define outl_p outl
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun #define inb_p inb
246*4882a593Smuzhiyun #define inw_p inw
247*4882a593Smuzhiyun #define inl_p inl
248*4882a593Smuzhiyun
insb(unsigned long port,void * buffer,int count)249*4882a593Smuzhiyun static inline void insb(unsigned long port, void *buffer, int count)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun if (count) {
252*4882a593Smuzhiyun u8 *buf = buffer;
253*4882a593Smuzhiyun do {
254*4882a593Smuzhiyun u8 x = inb(port);
255*4882a593Smuzhiyun *buf++ = x;
256*4882a593Smuzhiyun } while (--count);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
insw(unsigned long port,void * buffer,int count)260*4882a593Smuzhiyun static inline void insw(unsigned long port, void *buffer, int count)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun if (count) {
263*4882a593Smuzhiyun u16 *buf = buffer;
264*4882a593Smuzhiyun do {
265*4882a593Smuzhiyun u16 x = inw(port);
266*4882a593Smuzhiyun *buf++ = x;
267*4882a593Smuzhiyun } while (--count);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
insl(unsigned long port,void * buffer,int count)271*4882a593Smuzhiyun static inline void insl(unsigned long port, void *buffer, int count)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun if (count) {
274*4882a593Smuzhiyun u32 *buf = buffer;
275*4882a593Smuzhiyun do {
276*4882a593Smuzhiyun u32 x = inw(port);
277*4882a593Smuzhiyun *buf++ = x;
278*4882a593Smuzhiyun } while (--count);
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
outsb(unsigned long port,const void * buffer,int count)282*4882a593Smuzhiyun static inline void outsb(unsigned long port, const void *buffer, int count)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun if (count) {
285*4882a593Smuzhiyun const u8 *buf = buffer;
286*4882a593Smuzhiyun do {
287*4882a593Smuzhiyun outb(*buf++, port);
288*4882a593Smuzhiyun } while (--count);
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
outsw(unsigned long port,const void * buffer,int count)292*4882a593Smuzhiyun static inline void outsw(unsigned long port, const void *buffer, int count)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun if (count) {
295*4882a593Smuzhiyun const u16 *buf = buffer;
296*4882a593Smuzhiyun do {
297*4882a593Smuzhiyun outw(*buf++, port);
298*4882a593Smuzhiyun } while (--count);
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
outsl(unsigned long port,const void * buffer,int count)302*4882a593Smuzhiyun static inline void outsl(unsigned long port, const void *buffer, int count)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun if (count) {
305*4882a593Smuzhiyun const u32 *buf = buffer;
306*4882a593Smuzhiyun do {
307*4882a593Smuzhiyun outl(*buf++, port);
308*4882a593Smuzhiyun } while (--count);
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun #endif /* __KERNEL__ */
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun #endif
315