1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun compatible = "gnu,gdbsim"; 5*4882a593Smuzhiyun #address-cells = <1>; 6*4882a593Smuzhiyun #size-cells = <1>; 7*4882a593Smuzhiyun interrupt-parent = <&h8intc>; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun bootargs = "earlyprintk=h8300-sim"; 11*4882a593Smuzhiyun stdout-path = <&sci0>; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun serial0 = &sci0; 15*4882a593Smuzhiyun serial1 = &sci1; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun xclk: oscillator { 19*4882a593Smuzhiyun #clock-cells = <0>; 20*4882a593Smuzhiyun compatible = "fixed-clock"; 21*4882a593Smuzhiyun clock-frequency = <20000000>; 22*4882a593Smuzhiyun clock-output-names = "xtal"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun core_clk: core_clk { 25*4882a593Smuzhiyun compatible = "renesas,h8300-div-clock"; 26*4882a593Smuzhiyun clocks = <&xclk>; 27*4882a593Smuzhiyun #clock-cells = <0>; 28*4882a593Smuzhiyun reg = <0xfee01b 2>; 29*4882a593Smuzhiyun renesas,width = <2>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun fclk: fclk { 32*4882a593Smuzhiyun compatible = "fixed-factor-clock"; 33*4882a593Smuzhiyun clocks = <&core_clk>; 34*4882a593Smuzhiyun #clock-cells = <0>; 35*4882a593Smuzhiyun clock-div = <1>; 36*4882a593Smuzhiyun clock-mult = <1>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun memory@400000 { 40*4882a593Smuzhiyun device_type = "memory"; 41*4882a593Smuzhiyun reg = <0x400000 0x400000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun cpus { 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <0>; 47*4882a593Smuzhiyun cpu@0 { 48*4882a593Smuzhiyun compatible = "renesas,h8300"; 49*4882a593Smuzhiyun clock-frequency = <20000000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun h8intc: interrupt-controller@fee012 { 54*4882a593Smuzhiyun compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; 55*4882a593Smuzhiyun #interrupt-cells = <2>; 56*4882a593Smuzhiyun interrupt-controller; 57*4882a593Smuzhiyun reg = <0xfee012 7>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun bsc: memory-controller@fee01e { 61*4882a593Smuzhiyun compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; 62*4882a593Smuzhiyun reg = <0xfee01e 8>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun timer8: timer@ffff80 { 66*4882a593Smuzhiyun compatible = "renesas,8bit-timer"; 67*4882a593Smuzhiyun reg = <0xffff80 10>; 68*4882a593Smuzhiyun interrupts = <36 0>; 69*4882a593Smuzhiyun clocks = <&fclk>; 70*4882a593Smuzhiyun clock-names = "fck"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun timer16: timer@ffff68 { 74*4882a593Smuzhiyun compatible = "renesas,16bit-timer"; 75*4882a593Smuzhiyun reg = <0xffff68 8>, <0xffff60 8>; 76*4882a593Smuzhiyun interrupts = <26 0>; 77*4882a593Smuzhiyun renesas,channel = <0>; 78*4882a593Smuzhiyun clocks = <&fclk>; 79*4882a593Smuzhiyun clock-names = "fck"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun sci0: serial@ffffb0 { 83*4882a593Smuzhiyun compatible = "renesas,sci"; 84*4882a593Smuzhiyun reg = <0xffffb0 8>; 85*4882a593Smuzhiyun interrupts = <52 0>, <53 0>, <54 0>, <55 0>; 86*4882a593Smuzhiyun clocks = <&fclk>; 87*4882a593Smuzhiyun clock-names = "fck"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun sci1: serial@ffffb8 { 91*4882a593Smuzhiyun compatible = "renesas,sci"; 92*4882a593Smuzhiyun reg = <0xffffb8 8>; 93*4882a593Smuzhiyun interrupts = <56 0>, <57 0>, <58 0>, <59 0>; 94*4882a593Smuzhiyun clocks = <&fclk>; 95*4882a593Smuzhiyun clock-names = "fck"; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98