1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/cache.h>
5*4882a593Smuzhiyun #include <linux/dma-map-ops.h>
6*4882a593Smuzhiyun #include <linux/genalloc.h>
7*4882a593Smuzhiyun #include <linux/highmem.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/mm.h>
10*4882a593Smuzhiyun #include <linux/scatterlist.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/version.h>
13*4882a593Smuzhiyun #include <asm/cache.h>
14*4882a593Smuzhiyun
cache_op(phys_addr_t paddr,size_t size,void (* fn)(unsigned long start,unsigned long end))15*4882a593Smuzhiyun static inline void cache_op(phys_addr_t paddr, size_t size,
16*4882a593Smuzhiyun void (*fn)(unsigned long start, unsigned long end))
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun struct page *page = phys_to_page(paddr);
19*4882a593Smuzhiyun void *start = __va(page_to_phys(page));
20*4882a593Smuzhiyun unsigned long offset = offset_in_page(paddr);
21*4882a593Smuzhiyun size_t left = size;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun do {
24*4882a593Smuzhiyun size_t len = left;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (offset + len > PAGE_SIZE)
27*4882a593Smuzhiyun len = PAGE_SIZE - offset;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (PageHighMem(page)) {
30*4882a593Smuzhiyun start = kmap_atomic(page);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun fn((unsigned long)start + offset,
33*4882a593Smuzhiyun (unsigned long)start + offset + len);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun kunmap_atomic(start);
36*4882a593Smuzhiyun } else {
37*4882a593Smuzhiyun fn((unsigned long)start + offset,
38*4882a593Smuzhiyun (unsigned long)start + offset + len);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun offset = 0;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun page++;
43*4882a593Smuzhiyun start += PAGE_SIZE;
44*4882a593Smuzhiyun left -= len;
45*4882a593Smuzhiyun } while (left);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
dma_wbinv_set_zero_range(unsigned long start,unsigned long end)48*4882a593Smuzhiyun static void dma_wbinv_set_zero_range(unsigned long start, unsigned long end)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun memset((void *)start, 0, end - start);
51*4882a593Smuzhiyun dma_wbinv_range(start, end);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
arch_dma_prep_coherent(struct page * page,size_t size)54*4882a593Smuzhiyun void arch_dma_prep_coherent(struct page *page, size_t size)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun cache_op(page_to_phys(page), size, dma_wbinv_set_zero_range);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
arch_sync_dma_for_device(phys_addr_t paddr,size_t size,enum dma_data_direction dir)59*4882a593Smuzhiyun void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
60*4882a593Smuzhiyun enum dma_data_direction dir)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun switch (dir) {
63*4882a593Smuzhiyun case DMA_TO_DEVICE:
64*4882a593Smuzhiyun cache_op(paddr, size, dma_wb_range);
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun case DMA_FROM_DEVICE:
67*4882a593Smuzhiyun case DMA_BIDIRECTIONAL:
68*4882a593Smuzhiyun cache_op(paddr, size, dma_wbinv_range);
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun default:
71*4882a593Smuzhiyun BUG();
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
arch_sync_dma_for_cpu(phys_addr_t paddr,size_t size,enum dma_data_direction dir)75*4882a593Smuzhiyun void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
76*4882a593Smuzhiyun enum dma_data_direction dir)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun switch (dir) {
79*4882a593Smuzhiyun case DMA_TO_DEVICE:
80*4882a593Smuzhiyun return;
81*4882a593Smuzhiyun case DMA_FROM_DEVICE:
82*4882a593Smuzhiyun case DMA_BIDIRECTIONAL:
83*4882a593Smuzhiyun cache_op(paddr, size, dma_inv_range);
84*4882a593Smuzhiyun break;
85*4882a593Smuzhiyun default:
86*4882a593Smuzhiyun BUG();
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun }
89