1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __ASM_REGS_OPS_H 4*4882a593Smuzhiyun #define __ASM_REGS_OPS_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define mfcr(reg) \ 7*4882a593Smuzhiyun ({ \ 8*4882a593Smuzhiyun unsigned int tmp; \ 9*4882a593Smuzhiyun asm volatile( \ 10*4882a593Smuzhiyun "mfcr %0, "reg"\n" \ 11*4882a593Smuzhiyun : "=r"(tmp) \ 12*4882a593Smuzhiyun : \ 13*4882a593Smuzhiyun : "memory"); \ 14*4882a593Smuzhiyun tmp; \ 15*4882a593Smuzhiyun }) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define mtcr(reg, val) \ 18*4882a593Smuzhiyun ({ \ 19*4882a593Smuzhiyun asm volatile( \ 20*4882a593Smuzhiyun "mtcr %0, "reg"\n" \ 21*4882a593Smuzhiyun : \ 22*4882a593Smuzhiyun : "r"(val) \ 23*4882a593Smuzhiyun : "memory"); \ 24*4882a593Smuzhiyun }) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* __ASM_REGS_OPS_H */ 27