1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef __ASM_CSKY_MMU_CONTEXT_H
5*4882a593Smuzhiyun #define __ASM_CSKY_MMU_CONTEXT_H
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm-generic/mm_hooks.h>
8*4882a593Smuzhiyun #include <asm/setup.h>
9*4882a593Smuzhiyun #include <asm/page.h>
10*4882a593Smuzhiyun #include <asm/cacheflush.h>
11*4882a593Smuzhiyun #include <asm/tlbflush.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/sched.h>
15*4882a593Smuzhiyun #include <abi/ckmmu.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
18*4882a593Smuzhiyun setup_pgd(__pa(pgd), false)
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define TLBMISS_HANDLER_SETUP_PGD_KERNEL(pgd) \
21*4882a593Smuzhiyun setup_pgd(__pa(pgd), true)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define ASID_MASK ((1 << CONFIG_CPU_ASID_BITS) - 1)
24*4882a593Smuzhiyun #define cpu_asid(mm) (atomic64_read(&mm->context.asid) & ASID_MASK)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.asid, 0); 0; })
27*4882a593Smuzhiyun #define activate_mm(prev,next) switch_mm(prev, next, current)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define destroy_context(mm) do {} while (0)
30*4882a593Smuzhiyun #define enter_lazy_tlb(mm, tsk) do {} while (0)
31*4882a593Smuzhiyun #define deactivate_mm(tsk, mm) do {} while (0)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static inline void
switch_mm(struct mm_struct * prev,struct mm_struct * next,struct task_struct * tsk)36*4882a593Smuzhiyun switch_mm(struct mm_struct *prev, struct mm_struct *next,
37*4882a593Smuzhiyun struct task_struct *tsk)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun unsigned int cpu = smp_processor_id();
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (prev != next)
42*4882a593Smuzhiyun check_and_switch_context(next, cpu);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun TLBMISS_HANDLER_SETUP_PGD(next->pgd);
45*4882a593Smuzhiyun write_mmu_entryhi(next->context.asid.counter);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun flush_icache_deferred(next);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun #endif /* __ASM_CSKY_MMU_CONTEXT_H */
50