1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __ASM_CSKY_CACHE_H 4*4882a593Smuzhiyun #define __ASM_CSKY_CACHE_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* bytes per L1 cache line */ 7*4882a593Smuzhiyun #define L1_CACHE_SHIFT CONFIG_L1_CACHE_SHIFT 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun void dcache_wb_line(unsigned long start); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun void icache_inv_range(unsigned long start, unsigned long end); 18*4882a593Smuzhiyun void icache_inv_all(void); 19*4882a593Smuzhiyun void local_icache_inv_all(void *priv); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun void dcache_wb_range(unsigned long start, unsigned long end); 22*4882a593Smuzhiyun void dcache_wbinv_all(void); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun void cache_wbinv_range(unsigned long start, unsigned long end); 25*4882a593Smuzhiyun void cache_wbinv_all(void); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun void dma_wbinv_range(unsigned long start, unsigned long end); 28*4882a593Smuzhiyun void dma_inv_range(unsigned long start, unsigned long end); 29*4882a593Smuzhiyun void dma_wb_range(unsigned long start, unsigned long end); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun #endif /* __ASM_CSKY_CACHE_H */ 33