1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __ASM_CSKY_BARRIER_H 5*4882a593Smuzhiyun #define __ASM_CSKY_BARRIER_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define nop() asm volatile ("nop\n":::"memory") 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * sync: completion barrier, all sync.xx instructions 13*4882a593Smuzhiyun * guarantee the last response recieved by bus transaction 14*4882a593Smuzhiyun * made by ld/st instructions before sync.s 15*4882a593Smuzhiyun * sync.s: inherit from sync, but also shareable to other cores 16*4882a593Smuzhiyun * sync.i: inherit from sync, but also flush cpu pipeline 17*4882a593Smuzhiyun * sync.is: the same with sync.i + sync.s 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * bar.brwarw: ordering barrier for all load/store instructions before it 20*4882a593Smuzhiyun * bar.brwarws: ordering barrier for all load/store instructions before it 21*4882a593Smuzhiyun * and shareable to other cores 22*4882a593Smuzhiyun * bar.brar: ordering barrier for all load instructions before it 23*4882a593Smuzhiyun * bar.brars: ordering barrier for all load instructions before it 24*4882a593Smuzhiyun * and shareable to other cores 25*4882a593Smuzhiyun * bar.bwaw: ordering barrier for all store instructions before it 26*4882a593Smuzhiyun * bar.bwaws: ordering barrier for all store instructions before it 27*4882a593Smuzhiyun * and shareable to other cores 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifdef CONFIG_CPU_HAS_CACHEV2 31*4882a593Smuzhiyun #define mb() asm volatile ("sync.s\n":::"memory") 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #ifdef CONFIG_SMP 34*4882a593Smuzhiyun #define __smp_mb() asm volatile ("bar.brwarws\n":::"memory") 35*4882a593Smuzhiyun #define __smp_rmb() asm volatile ("bar.brars\n":::"memory") 36*4882a593Smuzhiyun #define __smp_wmb() asm volatile ("bar.bwaws\n":::"memory") 37*4882a593Smuzhiyun #endif /* CONFIG_SMP */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define sync_is() asm volatile ("sync.is\n":::"memory") 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #else /* !CONFIG_CPU_HAS_CACHEV2 */ 42*4882a593Smuzhiyun #define mb() asm volatile ("sync\n":::"memory") 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #include <asm-generic/barrier.h> 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 48*4882a593Smuzhiyun #endif /* __ASM_CSKY_BARRIER_H */ 49