1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __ASM_CSKY_REGDEF_H 5*4882a593Smuzhiyun #define __ASM_CSKY_REGDEF_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define syscallid r7 8*4882a593Smuzhiyun #define regs_syscallid(regs) regs->regs[3] 9*4882a593Smuzhiyun #define regs_fp(regs) regs->regs[4] 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * PSR format: 13*4882a593Smuzhiyun * | 31 | 30-24 | 23-16 | 15 14 | 13-10 | 9 | 8-0 | 14*4882a593Smuzhiyun * S VEC TM MM 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * S: Super Mode 17*4882a593Smuzhiyun * VEC: Exception Number 18*4882a593Smuzhiyun * TM: Trace Mode 19*4882a593Smuzhiyun * MM: Memory unaligned addr access 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define DEFAULT_PSR_VALUE 0x80000200 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SYSTRACE_SAVENUM 5 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define TRAP0_SIZE 4 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif /* __ASM_CSKY_REGDEF_H */ 28