1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __ASM_CSKY_FPU_H 5*4882a593Smuzhiyun #define __ASM_CSKY_FPU_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <asm/sigcontext.h> 8*4882a593Smuzhiyun #include <asm/ptrace.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun int fpu_libc_helper(struct pt_regs *regs); 11*4882a593Smuzhiyun void fpu_fpe(struct pt_regs *regs); 12*4882a593Smuzhiyun init_fpu(void)13*4882a593Smuzhiyunstatic inline void init_fpu(void) { mtcr("cr<1, 2>", 0); } 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun void save_to_user_fp(struct user_fp *user_fp); 16*4882a593Smuzhiyun void restore_from_user_fp(struct user_fp *user_fp); 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Define the fesr bit for fpe handle. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define FPE_ILLE (1 << 16) /* Illegal instruction */ 22*4882a593Smuzhiyun #define FPE_FEC (1 << 7) /* Input float-point arithmetic exception */ 23*4882a593Smuzhiyun #define FPE_IDC (1 << 5) /* Input denormalized exception */ 24*4882a593Smuzhiyun #define FPE_IXC (1 << 4) /* Inexact exception */ 25*4882a593Smuzhiyun #define FPE_UFC (1 << 3) /* Underflow exception */ 26*4882a593Smuzhiyun #define FPE_OFC (1 << 2) /* Overflow exception */ 27*4882a593Smuzhiyun #define FPE_DZC (1 << 1) /* Divide by zero exception */ 28*4882a593Smuzhiyun #define FPE_IOC (1 << 0) /* Invalid operation exception */ 29*4882a593Smuzhiyun #define FPE_REGULAR_EXCEPTION (FPE_IXC | FPE_UFC | FPE_OFC | FPE_DZC | FPE_IOC) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef CONFIG_OPEN_FPU_IDE 32*4882a593Smuzhiyun #define IDE_STAT (1 << 5) 33*4882a593Smuzhiyun #else 34*4882a593Smuzhiyun #define IDE_STAT 0 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #ifdef CONFIG_OPEN_FPU_IXE 38*4882a593Smuzhiyun #define IXE_STAT (1 << 4) 39*4882a593Smuzhiyun #else 40*4882a593Smuzhiyun #define IXE_STAT 0 41*4882a593Smuzhiyun #endif 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #ifdef CONFIG_OPEN_FPU_UFE 44*4882a593Smuzhiyun #define UFE_STAT (1 << 3) 45*4882a593Smuzhiyun #else 46*4882a593Smuzhiyun #define UFE_STAT 0 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #ifdef CONFIG_OPEN_FPU_OFE 50*4882a593Smuzhiyun #define OFE_STAT (1 << 2) 51*4882a593Smuzhiyun #else 52*4882a593Smuzhiyun #define OFE_STAT 0 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef CONFIG_OPEN_FPU_DZE 56*4882a593Smuzhiyun #define DZE_STAT (1 << 1) 57*4882a593Smuzhiyun #else 58*4882a593Smuzhiyun #define DZE_STAT 0 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #ifdef CONFIG_OPEN_FPU_IOE 62*4882a593Smuzhiyun #define IOE_STAT (1 << 0) 63*4882a593Smuzhiyun #else 64*4882a593Smuzhiyun #define IOE_STAT 0 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __ASM_CSKY_FPU_H */ 68