1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __ASM_CSKY_ENTRY_H 5*4882a593Smuzhiyun #define __ASM_CSKY_ENTRY_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <asm/setup.h> 8*4882a593Smuzhiyun #include <abi/regdef.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define LSAVE_PC 8 11*4882a593Smuzhiyun #define LSAVE_PSR 12 12*4882a593Smuzhiyun #define LSAVE_A0 24 13*4882a593Smuzhiyun #define LSAVE_A1 28 14*4882a593Smuzhiyun #define LSAVE_A2 32 15*4882a593Smuzhiyun #define LSAVE_A3 36 16*4882a593Smuzhiyun #define LSAVE_A4 40 17*4882a593Smuzhiyun #define LSAVE_A5 44 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define usp ss1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun .macro USPTOKSP 22*4882a593Smuzhiyun mtcr sp, usp 23*4882a593Smuzhiyun mfcr sp, ss0 24*4882a593Smuzhiyun .endm 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun .macro KSPTOUSP 27*4882a593Smuzhiyun mtcr sp, ss0 28*4882a593Smuzhiyun mfcr sp, usp 29*4882a593Smuzhiyun .endm 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun .macro SAVE_ALL epc_inc 32*4882a593Smuzhiyun mtcr r13, ss2 33*4882a593Smuzhiyun mfcr r13, epsr 34*4882a593Smuzhiyun btsti r13, 31 35*4882a593Smuzhiyun bt 1f 36*4882a593Smuzhiyun USPTOKSP 37*4882a593Smuzhiyun 1: 38*4882a593Smuzhiyun subi sp, 32 39*4882a593Smuzhiyun subi sp, 32 40*4882a593Smuzhiyun subi sp, 16 41*4882a593Smuzhiyun stw r13, (sp, 12) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun stw lr, (sp, 4) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun mfcr lr, epc 46*4882a593Smuzhiyun movi r13, \epc_inc 47*4882a593Smuzhiyun add lr, r13 48*4882a593Smuzhiyun stw lr, (sp, 8) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun mov lr, sp 51*4882a593Smuzhiyun addi lr, 32 52*4882a593Smuzhiyun addi lr, 32 53*4882a593Smuzhiyun addi lr, 16 54*4882a593Smuzhiyun bt 2f 55*4882a593Smuzhiyun mfcr lr, ss1 56*4882a593Smuzhiyun 2: 57*4882a593Smuzhiyun stw lr, (sp, 16) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun stw a0, (sp, 20) 60*4882a593Smuzhiyun stw a0, (sp, 24) 61*4882a593Smuzhiyun stw a1, (sp, 28) 62*4882a593Smuzhiyun stw a2, (sp, 32) 63*4882a593Smuzhiyun stw a3, (sp, 36) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun addi sp, 32 66*4882a593Smuzhiyun addi sp, 8 67*4882a593Smuzhiyun mfcr r13, ss2 68*4882a593Smuzhiyun stw r6, (sp) 69*4882a593Smuzhiyun stw r7, (sp, 4) 70*4882a593Smuzhiyun stw r8, (sp, 8) 71*4882a593Smuzhiyun stw r9, (sp, 12) 72*4882a593Smuzhiyun stw r10, (sp, 16) 73*4882a593Smuzhiyun stw r11, (sp, 20) 74*4882a593Smuzhiyun stw r12, (sp, 24) 75*4882a593Smuzhiyun stw r13, (sp, 28) 76*4882a593Smuzhiyun stw r14, (sp, 32) 77*4882a593Smuzhiyun stw r1, (sp, 36) 78*4882a593Smuzhiyun subi sp, 32 79*4882a593Smuzhiyun subi sp, 8 80*4882a593Smuzhiyun .endm 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun .macro RESTORE_ALL 83*4882a593Smuzhiyun ldw lr, (sp, 4) 84*4882a593Smuzhiyun ldw a0, (sp, 8) 85*4882a593Smuzhiyun mtcr a0, epc 86*4882a593Smuzhiyun ldw a0, (sp, 12) 87*4882a593Smuzhiyun mtcr a0, epsr 88*4882a593Smuzhiyun btsti a0, 31 89*4882a593Smuzhiyun bt 1f 90*4882a593Smuzhiyun ldw a0, (sp, 16) 91*4882a593Smuzhiyun mtcr a0, ss1 92*4882a593Smuzhiyun 1: 93*4882a593Smuzhiyun ldw a0, (sp, 24) 94*4882a593Smuzhiyun ldw a1, (sp, 28) 95*4882a593Smuzhiyun ldw a2, (sp, 32) 96*4882a593Smuzhiyun ldw a3, (sp, 36) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun addi sp, 32 99*4882a593Smuzhiyun addi sp, 8 100*4882a593Smuzhiyun ldw r6, (sp) 101*4882a593Smuzhiyun ldw r7, (sp, 4) 102*4882a593Smuzhiyun ldw r8, (sp, 8) 103*4882a593Smuzhiyun ldw r9, (sp, 12) 104*4882a593Smuzhiyun ldw r10, (sp, 16) 105*4882a593Smuzhiyun ldw r11, (sp, 20) 106*4882a593Smuzhiyun ldw r12, (sp, 24) 107*4882a593Smuzhiyun ldw r13, (sp, 28) 108*4882a593Smuzhiyun ldw r14, (sp, 32) 109*4882a593Smuzhiyun ldw r1, (sp, 36) 110*4882a593Smuzhiyun addi sp, 32 111*4882a593Smuzhiyun addi sp, 8 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun bt 2f 114*4882a593Smuzhiyun KSPTOUSP 115*4882a593Smuzhiyun 2: 116*4882a593Smuzhiyun rte 117*4882a593Smuzhiyun .endm 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun .macro SAVE_SWITCH_STACK 120*4882a593Smuzhiyun subi sp, 32 121*4882a593Smuzhiyun stm r8-r15, (sp) 122*4882a593Smuzhiyun .endm 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun .macro RESTORE_SWITCH_STACK 125*4882a593Smuzhiyun ldm r8-r15, (sp) 126*4882a593Smuzhiyun addi sp, 32 127*4882a593Smuzhiyun .endm 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* MMU registers operators. */ 130*4882a593Smuzhiyun .macro RD_MIR rx 131*4882a593Smuzhiyun cprcr \rx, cpcr0 132*4882a593Smuzhiyun .endm 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun .macro RD_MEH rx 135*4882a593Smuzhiyun cprcr \rx, cpcr4 136*4882a593Smuzhiyun .endm 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun .macro RD_MCIR rx 139*4882a593Smuzhiyun cprcr \rx, cpcr8 140*4882a593Smuzhiyun .endm 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun .macro RD_PGDR rx 143*4882a593Smuzhiyun cprcr \rx, cpcr29 144*4882a593Smuzhiyun .endm 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun .macro WR_MEH rx 147*4882a593Smuzhiyun cpwcr \rx, cpcr4 148*4882a593Smuzhiyun .endm 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun .macro WR_MCIR rx 151*4882a593Smuzhiyun cpwcr \rx, cpcr8 152*4882a593Smuzhiyun .endm 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun .macro SETUP_MMU 155*4882a593Smuzhiyun /* Init psr and enable ee */ 156*4882a593Smuzhiyun lrw r6, DEFAULT_PSR_VALUE 157*4882a593Smuzhiyun mtcr r6, psr 158*4882a593Smuzhiyun psrset ee 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* Select MMU as co-processor */ 161*4882a593Smuzhiyun cpseti cp15 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* 164*4882a593Smuzhiyun * cpcr30 format: 165*4882a593Smuzhiyun * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0 166*4882a593Smuzhiyun * BA Reserved C D V 167*4882a593Smuzhiyun */ 168*4882a593Smuzhiyun cprcr r6, cpcr30 169*4882a593Smuzhiyun lsri r6, 29 170*4882a593Smuzhiyun lsli r6, 29 171*4882a593Smuzhiyun addi r6, 0xe 172*4882a593Smuzhiyun cpwcr r6, cpcr30 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun movi r6, 0 175*4882a593Smuzhiyun cpwcr r6, cpcr31 176*4882a593Smuzhiyun .endm 177*4882a593Smuzhiyun #endif /* __ASM_CSKY_ENTRY_H */ 178