1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * External Memory Interface
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Incorporated
6*4882a593Smuzhiyun * Author: Mark Salter <msalter@redhat.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <asm/soc.h>
12*4882a593Smuzhiyun #include <asm/dscr.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define NUM_EMIFA_CHIP_ENABLES 4
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct emifa_regs {
17*4882a593Smuzhiyun u32 midr;
18*4882a593Smuzhiyun u32 stat;
19*4882a593Smuzhiyun u32 reserved1[6];
20*4882a593Smuzhiyun u32 bprio;
21*4882a593Smuzhiyun u32 reserved2[23];
22*4882a593Smuzhiyun u32 cecfg[NUM_EMIFA_CHIP_ENABLES];
23*4882a593Smuzhiyun u32 reserved3[4];
24*4882a593Smuzhiyun u32 awcc;
25*4882a593Smuzhiyun u32 reserved4[7];
26*4882a593Smuzhiyun u32 intraw;
27*4882a593Smuzhiyun u32 intmsk;
28*4882a593Smuzhiyun u32 intmskset;
29*4882a593Smuzhiyun u32 intmskclr;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static struct of_device_id emifa_match[] __initdata = {
33*4882a593Smuzhiyun { .compatible = "ti,c64x+emifa" },
34*4882a593Smuzhiyun {}
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Parse device tree for existence of an EMIF (External Memory Interface)
39*4882a593Smuzhiyun * and initialize it if found.
40*4882a593Smuzhiyun */
c6x_emifa_init(void)41*4882a593Smuzhiyun static int __init c6x_emifa_init(void)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct emifa_regs __iomem *regs;
44*4882a593Smuzhiyun struct device_node *node;
45*4882a593Smuzhiyun const __be32 *p;
46*4882a593Smuzhiyun u32 val;
47*4882a593Smuzhiyun int i, len, err;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun node = of_find_matching_node(NULL, emifa_match);
50*4882a593Smuzhiyun if (!node)
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun regs = of_iomap(node, 0);
54*4882a593Smuzhiyun if (!regs)
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* look for a dscr-based enable for emifa pin buffers */
58*4882a593Smuzhiyun err = of_property_read_u32_array(node, "ti,dscr-dev-enable", &val, 1);
59*4882a593Smuzhiyun if (!err)
60*4882a593Smuzhiyun dscr_set_devstate(val, DSCR_DEVSTATE_ENABLED);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* set up the chip enables */
63*4882a593Smuzhiyun p = of_get_property(node, "ti,emifa-ce-config", &len);
64*4882a593Smuzhiyun if (p) {
65*4882a593Smuzhiyun len /= sizeof(u32);
66*4882a593Smuzhiyun if (len > NUM_EMIFA_CHIP_ENABLES)
67*4882a593Smuzhiyun len = NUM_EMIFA_CHIP_ENABLES;
68*4882a593Smuzhiyun for (i = 0; i <= len; i++)
69*4882a593Smuzhiyun soc_writel(be32_to_cpup(&p[i]), ®s->cecfg[i]);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun err = of_property_read_u32_array(node, "ti,emifa-burst-priority", &val, 1);
73*4882a593Smuzhiyun if (!err)
74*4882a593Smuzhiyun soc_writel(val, ®s->bprio);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun err = of_property_read_u32_array(node, "ti,emifa-async-wait-control", &val, 1);
77*4882a593Smuzhiyun if (!err)
78*4882a593Smuzhiyun soc_writel(val, ®s->awcc);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun iounmap(regs);
81*4882a593Smuzhiyun of_node_put(node);
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun pure_initcall(c6x_emifa_init);
85