1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Port on Texas Instruments TMS320C6x architecture 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated 6*4882a593Smuzhiyun * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _ASM_C6X_SPECIAL_INSNS_H 9*4882a593Smuzhiyun #define _ASM_C6X_SPECIAL_INSNS_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define get_creg(reg) \ 13*4882a593Smuzhiyun ({ unsigned int __x; \ 14*4882a593Smuzhiyun asm volatile ("mvc .s2 " #reg ",%0\n" : "=b"(__x)); __x; }) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define set_creg(reg, v) \ 17*4882a593Smuzhiyun do { unsigned int __x = (unsigned int)(v); \ 18*4882a593Smuzhiyun asm volatile ("mvc .s2 %0," #reg "\n" : : "b"(__x)); \ 19*4882a593Smuzhiyun } while (0) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define or_creg(reg, n) \ 22*4882a593Smuzhiyun do { unsigned __x, __n = (unsigned)(n); \ 23*4882a593Smuzhiyun asm volatile ("mvc .s2 " #reg ",%0\n" \ 24*4882a593Smuzhiyun "or .l2 %1,%0,%0\n" \ 25*4882a593Smuzhiyun "mvc .s2 %0," #reg "\n" \ 26*4882a593Smuzhiyun "nop\n" \ 27*4882a593Smuzhiyun : "=&b"(__x) : "b"(__n)); \ 28*4882a593Smuzhiyun } while (0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define and_creg(reg, n) \ 31*4882a593Smuzhiyun do { unsigned __x, __n = (unsigned)(n); \ 32*4882a593Smuzhiyun asm volatile ("mvc .s2 " #reg ",%0\n" \ 33*4882a593Smuzhiyun "and .l2 %1,%0,%0\n" \ 34*4882a593Smuzhiyun "mvc .s2 %0," #reg "\n" \ 35*4882a593Smuzhiyun "nop\n" \ 36*4882a593Smuzhiyun : "=&b"(__x) : "b"(__n)); \ 37*4882a593Smuzhiyun } while (0) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define get_coreid() (get_creg(DNUM) & 0xff) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Set/get IST */ 42*4882a593Smuzhiyun #define set_ist(x) set_creg(ISTP, x) 43*4882a593Smuzhiyun #define get_ist() get_creg(ISTP) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Exception management 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define disable_exception() 49*4882a593Smuzhiyun #define get_except_type() get_creg(EFR) 50*4882a593Smuzhiyun #define ack_exception(type) set_creg(ECR, 1 << (type)) 51*4882a593Smuzhiyun #define get_iexcept() get_creg(IERR) 52*4882a593Smuzhiyun #define set_iexcept(mask) set_creg(IERR, (mask)) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define _extu(x, s, e) \ 55*4882a593Smuzhiyun ({ unsigned int __x; \ 56*4882a593Smuzhiyun asm volatile ("extu .S2 %3,%1,%2,%0\n" : \ 57*4882a593Smuzhiyun "=b"(__x) : "n"(s), "n"(e), "b"(x)); \ 58*4882a593Smuzhiyun __x; }) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* _ASM_C6X_SPECIAL_INSNS_H */ 61