1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Port on Texas Instruments TMS320C6x architecture 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated 6*4882a593Smuzhiyun * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _ASM_C6X_CACHE_H 9*4882a593Smuzhiyun #define _ASM_C6X_CACHE_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/irqflags.h> 12*4882a593Smuzhiyun #include <linux/init.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Cache line size 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define L1D_CACHE_SHIFT 6 18*4882a593Smuzhiyun #define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define L1P_CACHE_SHIFT 5 21*4882a593Smuzhiyun #define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define L2_CACHE_SHIFT 7 24*4882a593Smuzhiyun #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * L2 used as cache 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define L2MODE_SIZE L2MODE_256K_CACHE 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * For practical reasons the L1_CACHE_BYTES defines should not be smaller than 33*4882a593Smuzhiyun * the L2 line size 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define L1_CACHE_SHIFT L2_CACHE_SHIFT 36*4882a593Smuzhiyun #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define L2_CACHE_ALIGN_LOW(x) \ 39*4882a593Smuzhiyun (((x) & ~(L2_CACHE_BYTES - 1))) 40*4882a593Smuzhiyun #define L2_CACHE_ALIGN_UP(x) \ 41*4882a593Smuzhiyun (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1)) 42*4882a593Smuzhiyun #define L2_CACHE_ALIGN_CNT(x) \ 43*4882a593Smuzhiyun (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1)) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 46*4882a593Smuzhiyun #define ARCH_SLAB_MINALIGN L1_CACHE_BYTES 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * This is the granularity of hardware cacheability control. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define CACHEABILITY_ALIGN 0x01000000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * Align a physical address to MAR regions 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun #define CACHE_REGION_START(v) \ 57*4882a593Smuzhiyun (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1)) 58*4882a593Smuzhiyun #define CACHE_REGION_END(v) \ 59*4882a593Smuzhiyun (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1)) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun extern void __init c6x_cache_init(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun extern void enable_caching(unsigned long start, unsigned long end); 64*4882a593Smuzhiyun extern void disable_caching(unsigned long start, unsigned long end); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun extern void L1_cache_off(void); 67*4882a593Smuzhiyun extern void L1_cache_on(void); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun extern void L1P_cache_global_invalidate(void); 70*4882a593Smuzhiyun extern void L1D_cache_global_invalidate(void); 71*4882a593Smuzhiyun extern void L1D_cache_global_writeback(void); 72*4882a593Smuzhiyun extern void L1D_cache_global_writeback_invalidate(void); 73*4882a593Smuzhiyun extern void L2_cache_set_mode(unsigned int mode); 74*4882a593Smuzhiyun extern void L2_cache_global_writeback_invalidate(void); 75*4882a593Smuzhiyun extern void L2_cache_global_writeback(void); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end); 78*4882a593Smuzhiyun extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end); 79*4882a593Smuzhiyun extern void L1D_cache_block_writeback_invalidate(unsigned int start, 80*4882a593Smuzhiyun unsigned int end); 81*4882a593Smuzhiyun extern void L1D_cache_block_writeback(unsigned int start, unsigned int end); 82*4882a593Smuzhiyun extern void L2_cache_block_invalidate(unsigned int start, unsigned int end); 83*4882a593Smuzhiyun extern void L2_cache_block_writeback(unsigned int start, unsigned int end); 84*4882a593Smuzhiyun extern void L2_cache_block_writeback_invalidate(unsigned int start, 85*4882a593Smuzhiyun unsigned int end); 86*4882a593Smuzhiyun extern void L2_cache_block_invalidate_nowait(unsigned int start, 87*4882a593Smuzhiyun unsigned int end); 88*4882a593Smuzhiyun extern void L2_cache_block_writeback_nowait(unsigned int start, 89*4882a593Smuzhiyun unsigned int end); 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start, 92*4882a593Smuzhiyun unsigned int end); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* _ASM_C6X_CACHE_H */ 95