1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun #address-cells = <1>; 5*4882a593Smuzhiyun #size-cells = <1>; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <0>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun cpu@0 { 12*4882a593Smuzhiyun device_type = "cpu"; 13*4882a593Smuzhiyun model = "ti,c64x+"; 14*4882a593Smuzhiyun reg = <0>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun soc { 19*4882a593Smuzhiyun compatible = "simple-bus"; 20*4882a593Smuzhiyun model = "tms320c6457"; 21*4882a593Smuzhiyun #address-cells = <1>; 22*4882a593Smuzhiyun #size-cells = <1>; 23*4882a593Smuzhiyun ranges; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun core_pic: interrupt-controller { 26*4882a593Smuzhiyun interrupt-controller; 27*4882a593Smuzhiyun #interrupt-cells = <1>; 28*4882a593Smuzhiyun compatible = "ti,c64x+core-pic"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun megamod_pic: interrupt-controller@1800000 { 32*4882a593Smuzhiyun compatible = "ti,c64x+megamod-pic"; 33*4882a593Smuzhiyun interrupt-controller; 34*4882a593Smuzhiyun #interrupt-cells = <1>; 35*4882a593Smuzhiyun interrupt-parent = <&core_pic>; 36*4882a593Smuzhiyun reg = <0x1800000 0x1000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cache-controller@1840000 { 40*4882a593Smuzhiyun compatible = "ti,c64x+cache"; 41*4882a593Smuzhiyun reg = <0x01840000 0x8400>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun device-state-controller@2880800 { 45*4882a593Smuzhiyun compatible = "ti,c64x+dscr"; 46*4882a593Smuzhiyun reg = <0x02880800 0x400>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ti,dscr-devstat = <0x20>; 49*4882a593Smuzhiyun ti,dscr-silicon-rev = <0x18 28 0xf>; 50*4882a593Smuzhiyun ti,dscr-mac-fuse-regs = <0x114 3 4 5 6 51*4882a593Smuzhiyun 0x118 0 0 1 2>; 52*4882a593Smuzhiyun ti,dscr-kick-regs = <0x38 0x83E70B13 53*4882a593Smuzhiyun 0x3c 0x95A4F1E0>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun timer0: timer@2940000 { 57*4882a593Smuzhiyun compatible = "ti,c64x+timer64"; 58*4882a593Smuzhiyun reg = <0x2940000 0x40>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun clock-controller@29a0000 { 62*4882a593Smuzhiyun compatible = "ti,c6457-pll", "ti,c64x+pll"; 63*4882a593Smuzhiyun reg = <0x029a0000 0x200>; 64*4882a593Smuzhiyun ti,c64x+pll-bypass-delay = <300>; 65*4882a593Smuzhiyun ti,c64x+pll-reset-delay = <24000>; 66*4882a593Smuzhiyun ti,c64x+pll-lock-delay = <50000>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70