1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun #address-cells = <1>; 5*4882a593Smuzhiyun #size-cells = <1>; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <0>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun cpu@0 { 12*4882a593Smuzhiyun device_type = "cpu"; 13*4882a593Smuzhiyun model = "ti,c64x+"; 14*4882a593Smuzhiyun reg = <0>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun soc { 19*4882a593Smuzhiyun compatible = "simple-bus"; 20*4882a593Smuzhiyun model = "tms320c6455"; 21*4882a593Smuzhiyun #address-cells = <1>; 22*4882a593Smuzhiyun #size-cells = <1>; 23*4882a593Smuzhiyun ranges; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun core_pic: interrupt-controller { 26*4882a593Smuzhiyun interrupt-controller; 27*4882a593Smuzhiyun #interrupt-cells = <1>; 28*4882a593Smuzhiyun compatible = "ti,c64x+core-pic"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Megamodule interrupt controller 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun megamod_pic: interrupt-controller@1800000 { 35*4882a593Smuzhiyun compatible = "ti,c64x+megamod-pic"; 36*4882a593Smuzhiyun interrupt-controller; 37*4882a593Smuzhiyun #interrupt-cells = <1>; 38*4882a593Smuzhiyun reg = <0x1800000 0x1000>; 39*4882a593Smuzhiyun interrupt-parent = <&core_pic>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cache-controller@1840000 { 43*4882a593Smuzhiyun compatible = "ti,c64x+cache"; 44*4882a593Smuzhiyun reg = <0x01840000 0x8400>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun emifa@70000000 { 48*4882a593Smuzhiyun compatible = "ti,c64x+emifa", "simple-bus"; 49*4882a593Smuzhiyun #address-cells = <2>; 50*4882a593Smuzhiyun #size-cells = <1>; 51*4882a593Smuzhiyun reg = <0x70000000 0x100>; 52*4882a593Smuzhiyun ranges = <0x2 0x0 0xa0000000 0x00000008 53*4882a593Smuzhiyun 0x3 0x0 0xb0000000 0x00400000 54*4882a593Smuzhiyun 0x4 0x0 0xc0000000 0x10000000 55*4882a593Smuzhiyun 0x5 0x0 0xD0000000 0x10000000>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ti,dscr-dev-enable = <13>; 58*4882a593Smuzhiyun ti,emifa-burst-priority = <255>; 59*4882a593Smuzhiyun ti,emifa-ce-config = <0x00240120 60*4882a593Smuzhiyun 0x00240120 61*4882a593Smuzhiyun 0x00240122 62*4882a593Smuzhiyun 0x00240122>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun timer1: timer@2980000 { 66*4882a593Smuzhiyun compatible = "ti,c64x+timer64"; 67*4882a593Smuzhiyun reg = <0x2980000 0x40>; 68*4882a593Smuzhiyun ti,dscr-dev-enable = <4>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun clock-controller@029a0000 { 72*4882a593Smuzhiyun compatible = "ti,c6455-pll", "ti,c64x+pll"; 73*4882a593Smuzhiyun reg = <0x029a0000 0x200>; 74*4882a593Smuzhiyun ti,c64x+pll-bypass-delay = <1440>; 75*4882a593Smuzhiyun ti,c64x+pll-reset-delay = <15360>; 76*4882a593Smuzhiyun ti,c64x+pll-lock-delay = <24000>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun device-state-config-regs@2a80000 { 80*4882a593Smuzhiyun compatible = "ti,c64x+dscr"; 81*4882a593Smuzhiyun reg = <0x02a80000 0x41000>; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ti,dscr-devstat = <0>; 84*4882a593Smuzhiyun ti,dscr-silicon-rev = <8 28 0xf>; 85*4882a593Smuzhiyun ti,dscr-rmii-resets = <0 0x40020 0x00040000>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; 88*4882a593Smuzhiyun ti,dscr-devstate-ctl-regs = 89*4882a593Smuzhiyun <0 12 0x40008 1 0 0 2 90*4882a593Smuzhiyun 12 1 0x40008 3 0 30 2 91*4882a593Smuzhiyun 13 2 0x4002c 1 0xffffffff 0 1>; 92*4882a593Smuzhiyun ti,dscr-devstate-stat-regs = 93*4882a593Smuzhiyun <0 10 0x40014 1 0 0 3 94*4882a593Smuzhiyun 10 2 0x40018 1 0 0 3>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98