1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2012-2015 - ARM Ltd 4*4882a593Smuzhiyun * Author: Marc Zyngier <marc.zyngier@arm.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <clocksource/arm_arch_timer.h> 8*4882a593Smuzhiyun #include <linux/compiler.h> 9*4882a593Smuzhiyun #include <linux/kvm_host.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/kvm_hyp.h> 12*4882a593Smuzhiyun __kvm_timer_set_cntvoff(u64 cntvoff)13*4882a593Smuzhiyunvoid __kvm_timer_set_cntvoff(u64 cntvoff) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun write_sysreg(cntvoff, cntvoff_el2); 16*4882a593Smuzhiyun } 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Should only be called on non-VHE systems. 20*4882a593Smuzhiyun * VHE systems use EL2 timers and configure EL1 timers in kvm_timer_init_vhe(). 21*4882a593Smuzhiyun */ __timer_disable_traps(struct kvm_vcpu * vcpu)22*4882a593Smuzhiyunvoid __timer_disable_traps(struct kvm_vcpu *vcpu) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun u64 val; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Allow physical timer/counter access for the host */ 27*4882a593Smuzhiyun val = read_sysreg(cnthctl_el2); 28*4882a593Smuzhiyun val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN; 29*4882a593Smuzhiyun write_sysreg(val, cnthctl_el2); 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Should only be called on non-VHE systems. 34*4882a593Smuzhiyun * VHE systems use EL2 timers and configure EL1 timers in kvm_timer_init_vhe(). 35*4882a593Smuzhiyun */ __timer_enable_traps(struct kvm_vcpu * vcpu)36*4882a593Smuzhiyunvoid __timer_enable_traps(struct kvm_vcpu *vcpu) 37*4882a593Smuzhiyun { 38*4882a593Smuzhiyun u64 val; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * Disallow physical timer access for the guest 42*4882a593Smuzhiyun * Physical counter access is allowed 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun val = read_sysreg(cnthctl_el2); 45*4882a593Smuzhiyun val &= ~CNTHCTL_EL1PCEN; 46*4882a593Smuzhiyun val |= CNTHCTL_EL1PCTEN; 47*4882a593Smuzhiyun write_sysreg(val, cnthctl_el2); 48*4882a593Smuzhiyun } 49