1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2012 ARM Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #ifndef __ASM_MODULE_H
6*4882a593Smuzhiyun #define __ASM_MODULE_H
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm-generic/module.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifdef CONFIG_ARM64_MODULE_PLTS
11*4882a593Smuzhiyun struct mod_plt_sec {
12*4882a593Smuzhiyun int plt_shndx;
13*4882a593Smuzhiyun int plt_num_entries;
14*4882a593Smuzhiyun int plt_max_entries;
15*4882a593Smuzhiyun };
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct mod_arch_specific {
18*4882a593Smuzhiyun struct mod_plt_sec core;
19*4882a593Smuzhiyun struct mod_plt_sec init;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* for CONFIG_DYNAMIC_FTRACE */
22*4882a593Smuzhiyun struct plt_entry *ftrace_trampolines;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* for FIPS 140 certified kernel module */
25*4882a593Smuzhiyun const Elf64_Rela *text_relocations;
26*4882a593Smuzhiyun const Elf64_Rela *rodata_relocations;
27*4882a593Smuzhiyun int num_text_relocations;
28*4882a593Smuzhiyun int num_rodata_relocations;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs,
33*4882a593Smuzhiyun void *loc, const Elf64_Rela *rela,
34*4882a593Smuzhiyun Elf64_Sym *sym);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs,
37*4882a593Smuzhiyun void *loc, u64 val);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #ifdef CONFIG_RANDOMIZE_BASE
40*4882a593Smuzhiyun extern u64 module_alloc_base;
41*4882a593Smuzhiyun #else
42*4882a593Smuzhiyun #define module_alloc_base ((u64)_etext - MODULES_VSIZE)
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct plt_entry {
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * A program that conforms to the AArch64 Procedure Call Standard
48*4882a593Smuzhiyun * (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
49*4882a593Smuzhiyun * IP1 (x17) may be inserted at any branch instruction that is
50*4882a593Smuzhiyun * exposed to a relocation that supports long branches. Since that
51*4882a593Smuzhiyun * is exactly what we are dealing with here, we are free to use x16
52*4882a593Smuzhiyun * as a scratch register in the PLT veneers.
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun __le32 adrp; /* adrp x16, .... */
55*4882a593Smuzhiyun __le32 add; /* add x16, x16, #0x.... */
56*4882a593Smuzhiyun __le32 br; /* br x16 */
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
is_forbidden_offset_for_adrp(void * place)59*4882a593Smuzhiyun static inline bool is_forbidden_offset_for_adrp(void *place)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) &&
62*4882a593Smuzhiyun cpus_have_const_cap(ARM64_WORKAROUND_843419) &&
63*4882a593Smuzhiyun ((u64)place & 0xfff) >= 0xff8;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun struct plt_entry get_plt_entry(u64 dst, void *pc);
67*4882a593Smuzhiyun bool plt_entries_equal(const struct plt_entry *a, const struct plt_entry *b);
68*4882a593Smuzhiyun
plt_entry_is_initialized(const struct plt_entry * e)69*4882a593Smuzhiyun static inline bool plt_entry_is_initialized(const struct plt_entry *e)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun return e->adrp || e->add || e->br;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #endif /* __ASM_MODULE_H */
75