1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2012 ARM Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #ifndef __ASM_HW_BREAKPOINT_H
6*4882a593Smuzhiyun #define __ASM_HW_BREAKPOINT_H
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm/cputype.h>
9*4882a593Smuzhiyun #include <asm/cpufeature.h>
10*4882a593Smuzhiyun #include <asm/sysreg.h>
11*4882a593Smuzhiyun #include <asm/virt.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl {
14*4882a593Smuzhiyun u32 __reserved : 19,
15*4882a593Smuzhiyun len : 8,
16*4882a593Smuzhiyun type : 2,
17*4882a593Smuzhiyun privilege : 2,
18*4882a593Smuzhiyun enabled : 1;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct arch_hw_breakpoint {
22*4882a593Smuzhiyun u64 address;
23*4882a593Smuzhiyun u64 trigger;
24*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl ctrl;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Privilege Levels */
28*4882a593Smuzhiyun #define AARCH64_BREAKPOINT_EL1 1
29*4882a593Smuzhiyun #define AARCH64_BREAKPOINT_EL0 2
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define DBG_HMC_HYP (1 << 13)
32*4882a593Smuzhiyun
encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)33*4882a593Smuzhiyun static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
36*4882a593Smuzhiyun ctrl.enabled;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
39*4882a593Smuzhiyun val |= DBG_HMC_HYP;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return val;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
decode_ctrl_reg(u32 reg,struct arch_hw_breakpoint_ctrl * ctrl)44*4882a593Smuzhiyun static inline void decode_ctrl_reg(u32 reg,
45*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl *ctrl)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun ctrl->enabled = reg & 0x1;
48*4882a593Smuzhiyun reg >>= 1;
49*4882a593Smuzhiyun ctrl->privilege = reg & 0x3;
50*4882a593Smuzhiyun reg >>= 2;
51*4882a593Smuzhiyun ctrl->type = reg & 0x3;
52*4882a593Smuzhiyun reg >>= 2;
53*4882a593Smuzhiyun ctrl->len = reg & 0xff;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Breakpoint */
57*4882a593Smuzhiyun #define ARM_BREAKPOINT_EXECUTE 0
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Watchpoints */
60*4882a593Smuzhiyun #define ARM_BREAKPOINT_LOAD 1
61*4882a593Smuzhiyun #define ARM_BREAKPOINT_STORE 2
62*4882a593Smuzhiyun #define AARCH64_ESR_ACCESS_MASK (1 << 6)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Lengths */
65*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_1 0x1
66*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_2 0x3
67*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_3 0x7
68*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_4 0xf
69*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_5 0x1f
70*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_6 0x3f
71*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_7 0x7f
72*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_8 0xff
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Kernel stepping */
75*4882a593Smuzhiyun #define ARM_KERNEL_STEP_NONE 0
76*4882a593Smuzhiyun #define ARM_KERNEL_STEP_ACTIVE 1
77*4882a593Smuzhiyun #define ARM_KERNEL_STEP_SUSPEND 2
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * Limits.
81*4882a593Smuzhiyun * Changing these will require modifications to the register accessors.
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun #define ARM_MAX_BRP 16
84*4882a593Smuzhiyun #define ARM_MAX_WRP 16
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Virtual debug register bases. */
87*4882a593Smuzhiyun #define AARCH64_DBG_REG_BVR 0
88*4882a593Smuzhiyun #define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
89*4882a593Smuzhiyun #define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
90*4882a593Smuzhiyun #define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Debug register names. */
93*4882a593Smuzhiyun #define AARCH64_DBG_REG_NAME_BVR bvr
94*4882a593Smuzhiyun #define AARCH64_DBG_REG_NAME_BCR bcr
95*4882a593Smuzhiyun #define AARCH64_DBG_REG_NAME_WVR wvr
96*4882a593Smuzhiyun #define AARCH64_DBG_REG_NAME_WCR wcr
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Accessor macros for the debug registers. */
99*4882a593Smuzhiyun #define AARCH64_DBG_READ(N, REG, VAL) do {\
100*4882a593Smuzhiyun VAL = read_sysreg(dbg##REG##N##_el1);\
101*4882a593Smuzhiyun } while (0)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
104*4882a593Smuzhiyun write_sysreg(VAL, dbg##REG##N##_el1);\
105*4882a593Smuzhiyun } while (0)
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun struct task_struct;
108*4882a593Smuzhiyun struct notifier_block;
109*4882a593Smuzhiyun struct perf_event_attr;
110*4882a593Smuzhiyun struct perf_event;
111*4882a593Smuzhiyun struct pmu;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
114*4882a593Smuzhiyun int *gen_len, int *gen_type, int *offset);
115*4882a593Smuzhiyun extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
116*4882a593Smuzhiyun extern int hw_breakpoint_arch_parse(struct perf_event *bp,
117*4882a593Smuzhiyun const struct perf_event_attr *attr,
118*4882a593Smuzhiyun struct arch_hw_breakpoint *hw);
119*4882a593Smuzhiyun extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
120*4882a593Smuzhiyun unsigned long val, void *data);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun extern int arch_install_hw_breakpoint(struct perf_event *bp);
123*4882a593Smuzhiyun extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
124*4882a593Smuzhiyun extern void hw_breakpoint_pmu_read(struct perf_event *bp);
125*4882a593Smuzhiyun extern int hw_breakpoint_slots(int type);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #ifdef CONFIG_HAVE_HW_BREAKPOINT
128*4882a593Smuzhiyun extern void hw_breakpoint_thread_switch(struct task_struct *next);
129*4882a593Smuzhiyun extern void ptrace_hw_copy_thread(struct task_struct *task);
130*4882a593Smuzhiyun #else
hw_breakpoint_thread_switch(struct task_struct * next)131*4882a593Smuzhiyun static inline void hw_breakpoint_thread_switch(struct task_struct *next)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun }
ptrace_hw_copy_thread(struct task_struct * task)134*4882a593Smuzhiyun static inline void ptrace_hw_copy_thread(struct task_struct *task)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun #endif
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* Determine number of BRP registers available. */
get_num_brps(void)140*4882a593Smuzhiyun static inline int get_num_brps(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
143*4882a593Smuzhiyun return 1 +
144*4882a593Smuzhiyun cpuid_feature_extract_unsigned_field(dfr0,
145*4882a593Smuzhiyun ID_AA64DFR0_BRPS_SHIFT);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* Determine number of WRP registers available. */
get_num_wrps(void)149*4882a593Smuzhiyun static inline int get_num_wrps(void)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
152*4882a593Smuzhiyun return 1 +
153*4882a593Smuzhiyun cpuid_feature_extract_unsigned_field(dfr0,
154*4882a593Smuzhiyun ID_AA64DFR0_WRPS_SHIFT);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #endif /* __ASM_BREAKPOINT_H */
158