1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm64/include/asm/cpucaps.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 ARM Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPUCAPS_H 8*4882a593Smuzhiyun #define __ASM_CPUCAPS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define ARM64_WORKAROUND_CLEAN_CACHE 0 11*4882a593Smuzhiyun #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 12*4882a593Smuzhiyun #define ARM64_WORKAROUND_845719 2 13*4882a593Smuzhiyun #define ARM64_HAS_SYSREG_GIC_CPUIF 3 14*4882a593Smuzhiyun #define ARM64_HAS_PAN 4 15*4882a593Smuzhiyun #define ARM64_HAS_LSE_ATOMICS 5 16*4882a593Smuzhiyun #define ARM64_WORKAROUND_CAVIUM_23154 6 17*4882a593Smuzhiyun #define ARM64_WORKAROUND_834220 7 18*4882a593Smuzhiyun #define ARM64_HAS_NO_HW_PREFETCH 8 19*4882a593Smuzhiyun #define ARM64_HAS_UAO 9 20*4882a593Smuzhiyun #define ARM64_ALT_PAN_NOT_UAO 10 21*4882a593Smuzhiyun #define ARM64_HAS_VIRT_HOST_EXTN 11 22*4882a593Smuzhiyun #define ARM64_WORKAROUND_CAVIUM_27456 12 23*4882a593Smuzhiyun /* Unreliable: use system_supports_32bit_el0() instead. */ 24*4882a593Smuzhiyun #define ARM64_HAS_32BIT_EL0_DO_NOT_USE 13 25*4882a593Smuzhiyun #define ARM64_SPECTRE_V3A 14 26*4882a593Smuzhiyun #define ARM64_HAS_CNP 15 27*4882a593Smuzhiyun #define ARM64_HAS_NO_FPSIMD 16 28*4882a593Smuzhiyun #define ARM64_WORKAROUND_REPEAT_TLBI 17 29*4882a593Smuzhiyun #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 30*4882a593Smuzhiyun #define ARM64_WORKAROUND_858921 19 31*4882a593Smuzhiyun #define ARM64_WORKAROUND_CAVIUM_30115 20 32*4882a593Smuzhiyun #define ARM64_HAS_DCPOP 21 33*4882a593Smuzhiyun #define ARM64_SVE 22 34*4882a593Smuzhiyun #define ARM64_UNMAP_KERNEL_AT_EL0 23 35*4882a593Smuzhiyun #define ARM64_SPECTRE_V2 24 36*4882a593Smuzhiyun #define ARM64_HAS_RAS_EXTN 25 37*4882a593Smuzhiyun #define ARM64_WORKAROUND_843419 26 38*4882a593Smuzhiyun #define ARM64_HAS_CACHE_IDC 27 39*4882a593Smuzhiyun #define ARM64_HAS_CACHE_DIC 28 40*4882a593Smuzhiyun #define ARM64_HW_DBM 29 41*4882a593Smuzhiyun #define ARM64_SPECTRE_V4 30 42*4882a593Smuzhiyun #define ARM64_MISMATCHED_CACHE_TYPE 31 43*4882a593Smuzhiyun #define ARM64_HAS_STAGE2_FWB 32 44*4882a593Smuzhiyun #define ARM64_HAS_CRC32 33 45*4882a593Smuzhiyun #define ARM64_SSBS 34 46*4882a593Smuzhiyun #define ARM64_WORKAROUND_1418040 35 47*4882a593Smuzhiyun #define ARM64_HAS_SB 36 48*4882a593Smuzhiyun #define ARM64_WORKAROUND_SPECULATIVE_AT 37 49*4882a593Smuzhiyun #define ARM64_HAS_ADDRESS_AUTH_ARCH 38 50*4882a593Smuzhiyun #define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39 51*4882a593Smuzhiyun #define ARM64_HAS_GENERIC_AUTH_ARCH 40 52*4882a593Smuzhiyun #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 53*4882a593Smuzhiyun #define ARM64_HAS_IRQ_PRIO_MASKING 42 54*4882a593Smuzhiyun #define ARM64_HAS_DCPODP 43 55*4882a593Smuzhiyun #define ARM64_WORKAROUND_1463225 44 56*4882a593Smuzhiyun #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 57*4882a593Smuzhiyun #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 58*4882a593Smuzhiyun #define ARM64_WORKAROUND_1542419 47 59*4882a593Smuzhiyun #define ARM64_HAS_E0PD 48 60*4882a593Smuzhiyun #define ARM64_HAS_RNG 49 61*4882a593Smuzhiyun #define ARM64_HAS_AMU_EXTN 50 62*4882a593Smuzhiyun #define ARM64_HAS_ADDRESS_AUTH 51 63*4882a593Smuzhiyun #define ARM64_HAS_GENERIC_AUTH 52 64*4882a593Smuzhiyun #define ARM64_HAS_32BIT_EL1 53 65*4882a593Smuzhiyun #define ARM64_BTI 54 66*4882a593Smuzhiyun #define ARM64_HAS_ARMv8_4_TTL 55 67*4882a593Smuzhiyun #define ARM64_HAS_TLB_RANGE 56 68*4882a593Smuzhiyun #define ARM64_MTE 57 69*4882a593Smuzhiyun #define ARM64_WORKAROUND_1508412 58 70*4882a593Smuzhiyun #define ARM64_HAS_LDAPR 59 71*4882a593Smuzhiyun #define ARM64_KVM_PROTECTED_MODE 60 72*4882a593Smuzhiyun #define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 61 73*4882a593Smuzhiyun #define ARM64_SPECTRE_BHB 62 74*4882a593Smuzhiyun #define ARM64_WORKAROUND_2457168 63 75*4882a593Smuzhiyun #define ARM64_WORKAROUND_1742098 64 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* kabi: reserve 65 - 76 for future cpu capabilities */ 78*4882a593Smuzhiyun #define ARM64_NCAPS 76 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif /* __ASM_CPUCAPS_H */ 81