1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ASM_UACCESS_H 3*4882a593Smuzhiyun #define __ASM_ASM_UACCESS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/alternative-macros.h> 6*4882a593Smuzhiyun #include <asm/kernel-pgtable.h> 7*4882a593Smuzhiyun #include <asm/mmu.h> 8*4882a593Smuzhiyun #include <asm/sysreg.h> 9*4882a593Smuzhiyun #include <asm/assembler.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * User access enabling/disabling macros. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifdef CONFIG_ARM64_SW_TTBR0_PAN 15*4882a593Smuzhiyun .macro __uaccess_ttbr0_disable, tmp1 16*4882a593Smuzhiyun mrs \tmp1, ttbr1_el1 // swapper_pg_dir 17*4882a593Smuzhiyun bic \tmp1, \tmp1, #TTBR_ASID_MASK 18*4882a593Smuzhiyun sub \tmp1, \tmp1, #PAGE_SIZE // reserved_pg_dir just before swapper_pg_dir 19*4882a593Smuzhiyun msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 20*4882a593Smuzhiyun isb 21*4882a593Smuzhiyun add \tmp1, \tmp1, #PAGE_SIZE 22*4882a593Smuzhiyun msr ttbr1_el1, \tmp1 // set reserved ASID 23*4882a593Smuzhiyun isb 24*4882a593Smuzhiyun .endm 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun .macro __uaccess_ttbr0_enable, tmp1, tmp2 27*4882a593Smuzhiyun get_current_task \tmp1 28*4882a593Smuzhiyun ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 29*4882a593Smuzhiyun mrs \tmp2, ttbr1_el1 30*4882a593Smuzhiyun extr \tmp2, \tmp2, \tmp1, #48 31*4882a593Smuzhiyun ror \tmp2, \tmp2, #16 32*4882a593Smuzhiyun msr ttbr1_el1, \tmp2 // set the active ASID 33*4882a593Smuzhiyun isb 34*4882a593Smuzhiyun msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 35*4882a593Smuzhiyun isb 36*4882a593Smuzhiyun .endm 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun .macro uaccess_ttbr0_disable, tmp1, tmp2 39*4882a593Smuzhiyun alternative_if_not ARM64_HAS_PAN 40*4882a593Smuzhiyun save_and_disable_irq \tmp2 // avoid preemption 41*4882a593Smuzhiyun __uaccess_ttbr0_disable \tmp1 42*4882a593Smuzhiyun restore_irq \tmp2 43*4882a593Smuzhiyun alternative_else_nop_endif 44*4882a593Smuzhiyun .endm 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 47*4882a593Smuzhiyun alternative_if_not ARM64_HAS_PAN 48*4882a593Smuzhiyun save_and_disable_irq \tmp3 // avoid preemption 49*4882a593Smuzhiyun __uaccess_ttbr0_enable \tmp1, \tmp2 50*4882a593Smuzhiyun restore_irq \tmp3 51*4882a593Smuzhiyun alternative_else_nop_endif 52*4882a593Smuzhiyun .endm 53*4882a593Smuzhiyun #else 54*4882a593Smuzhiyun .macro uaccess_ttbr0_disable, tmp1, tmp2 55*4882a593Smuzhiyun .endm 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 58*4882a593Smuzhiyun .endm 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * Generate the assembly for LDTR/STTR with exception table entries. 63*4882a593Smuzhiyun * This is complicated as there is no post-increment or pair versions of the 64*4882a593Smuzhiyun * unprivileged instructions, and USER() only works for single instructions. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun .macro uao_ldp l, reg1, reg2, addr, post_inc 67*4882a593Smuzhiyun 8888: ldtr \reg1, [\addr]; 68*4882a593Smuzhiyun 8889: ldtr \reg2, [\addr, #8]; 69*4882a593Smuzhiyun add \addr, \addr, \post_inc; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun _asm_extable 8888b,\l; 72*4882a593Smuzhiyun _asm_extable 8889b,\l; 73*4882a593Smuzhiyun .endm 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun .macro uao_stp l, reg1, reg2, addr, post_inc 76*4882a593Smuzhiyun 8888: sttr \reg1, [\addr]; 77*4882a593Smuzhiyun 8889: sttr \reg2, [\addr, #8]; 78*4882a593Smuzhiyun add \addr, \addr, \post_inc; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun _asm_extable 8888b,\l; 81*4882a593Smuzhiyun _asm_extable 8889b,\l; 82*4882a593Smuzhiyun .endm 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc 85*4882a593Smuzhiyun 8888: \alt_inst \reg, [\addr]; 86*4882a593Smuzhiyun add \addr, \addr, \post_inc; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun _asm_extable 8888b,\l; 89*4882a593Smuzhiyun .endm 90*4882a593Smuzhiyun #endif 91