1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ARM DynamIQ Shared Unit (DSU) PMU Low level register access routines.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) ARM Limited, 2017.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/build_bug.h>
12*4882a593Smuzhiyun #include <linux/compiler.h>
13*4882a593Smuzhiyun #include <linux/types.h>
14*4882a593Smuzhiyun #include <asm/barrier.h>
15*4882a593Smuzhiyun #include <asm/sysreg.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define CLUSTERPMCR_EL1 sys_reg(3, 0, 15, 5, 0)
19*4882a593Smuzhiyun #define CLUSTERPMCNTENSET_EL1 sys_reg(3, 0, 15, 5, 1)
20*4882a593Smuzhiyun #define CLUSTERPMCNTENCLR_EL1 sys_reg(3, 0, 15, 5, 2)
21*4882a593Smuzhiyun #define CLUSTERPMOVSSET_EL1 sys_reg(3, 0, 15, 5, 3)
22*4882a593Smuzhiyun #define CLUSTERPMOVSCLR_EL1 sys_reg(3, 0, 15, 5, 4)
23*4882a593Smuzhiyun #define CLUSTERPMSELR_EL1 sys_reg(3, 0, 15, 5, 5)
24*4882a593Smuzhiyun #define CLUSTERPMINTENSET_EL1 sys_reg(3, 0, 15, 5, 6)
25*4882a593Smuzhiyun #define CLUSTERPMINTENCLR_EL1 sys_reg(3, 0, 15, 5, 7)
26*4882a593Smuzhiyun #define CLUSTERPMCCNTR_EL1 sys_reg(3, 0, 15, 6, 0)
27*4882a593Smuzhiyun #define CLUSTERPMXEVTYPER_EL1 sys_reg(3, 0, 15, 6, 1)
28*4882a593Smuzhiyun #define CLUSTERPMXEVCNTR_EL1 sys_reg(3, 0, 15, 6, 2)
29*4882a593Smuzhiyun #define CLUSTERPMMDCR_EL1 sys_reg(3, 0, 15, 6, 3)
30*4882a593Smuzhiyun #define CLUSTERPMCEID0_EL1 sys_reg(3, 0, 15, 6, 4)
31*4882a593Smuzhiyun #define CLUSTERPMCEID1_EL1 sys_reg(3, 0, 15, 6, 5)
32*4882a593Smuzhiyun
__dsu_pmu_read_pmcr(void)33*4882a593Smuzhiyun static inline u32 __dsu_pmu_read_pmcr(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun return read_sysreg_s(CLUSTERPMCR_EL1);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
__dsu_pmu_write_pmcr(u32 val)38*4882a593Smuzhiyun static inline void __dsu_pmu_write_pmcr(u32 val)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun write_sysreg_s(val, CLUSTERPMCR_EL1);
41*4882a593Smuzhiyun isb();
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
__dsu_pmu_get_reset_overflow(void)44*4882a593Smuzhiyun static inline u32 __dsu_pmu_get_reset_overflow(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun u32 val = read_sysreg_s(CLUSTERPMOVSCLR_EL1);
47*4882a593Smuzhiyun /* Clear the bit */
48*4882a593Smuzhiyun write_sysreg_s(val, CLUSTERPMOVSCLR_EL1);
49*4882a593Smuzhiyun isb();
50*4882a593Smuzhiyun return val;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
__dsu_pmu_select_counter(int counter)53*4882a593Smuzhiyun static inline void __dsu_pmu_select_counter(int counter)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun write_sysreg_s(counter, CLUSTERPMSELR_EL1);
56*4882a593Smuzhiyun isb();
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
__dsu_pmu_read_counter(int counter)59*4882a593Smuzhiyun static inline u64 __dsu_pmu_read_counter(int counter)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun __dsu_pmu_select_counter(counter);
62*4882a593Smuzhiyun return read_sysreg_s(CLUSTERPMXEVCNTR_EL1);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
__dsu_pmu_write_counter(int counter,u64 val)65*4882a593Smuzhiyun static inline void __dsu_pmu_write_counter(int counter, u64 val)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun __dsu_pmu_select_counter(counter);
68*4882a593Smuzhiyun write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1);
69*4882a593Smuzhiyun isb();
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
__dsu_pmu_set_event(int counter,u32 event)72*4882a593Smuzhiyun static inline void __dsu_pmu_set_event(int counter, u32 event)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun __dsu_pmu_select_counter(counter);
75*4882a593Smuzhiyun write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1);
76*4882a593Smuzhiyun isb();
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
__dsu_pmu_read_pmccntr(void)79*4882a593Smuzhiyun static inline u64 __dsu_pmu_read_pmccntr(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun return read_sysreg_s(CLUSTERPMCCNTR_EL1);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
__dsu_pmu_write_pmccntr(u64 val)84*4882a593Smuzhiyun static inline void __dsu_pmu_write_pmccntr(u64 val)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun write_sysreg_s(val, CLUSTERPMCCNTR_EL1);
87*4882a593Smuzhiyun isb();
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
__dsu_pmu_disable_counter(int counter)90*4882a593Smuzhiyun static inline void __dsu_pmu_disable_counter(int counter)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1);
93*4882a593Smuzhiyun isb();
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
__dsu_pmu_enable_counter(int counter)96*4882a593Smuzhiyun static inline void __dsu_pmu_enable_counter(int counter)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1);
99*4882a593Smuzhiyun isb();
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
__dsu_pmu_counter_interrupt_enable(int counter)102*4882a593Smuzhiyun static inline void __dsu_pmu_counter_interrupt_enable(int counter)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1);
105*4882a593Smuzhiyun isb();
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
__dsu_pmu_counter_interrupt_disable(int counter)108*4882a593Smuzhiyun static inline void __dsu_pmu_counter_interrupt_disable(int counter)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1);
111*4882a593Smuzhiyun isb();
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun
__dsu_pmu_read_pmceid(int n)115*4882a593Smuzhiyun static inline u32 __dsu_pmu_read_pmceid(int n)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun switch (n) {
118*4882a593Smuzhiyun case 0:
119*4882a593Smuzhiyun return read_sysreg_s(CLUSTERPMCEID0_EL1);
120*4882a593Smuzhiyun case 1:
121*4882a593Smuzhiyun return read_sysreg_s(CLUSTERPMCEID1_EL1);
122*4882a593Smuzhiyun default:
123*4882a593Smuzhiyun BUILD_BUG();
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun }
127