xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/zte/zx296718-pcbox.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2017 Sanechips Technology Co., Ltd.
3*4882a593Smuzhiyun * Copyright 2017 Linaro Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun#include "zx296718.dtsi"
10*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "ZTE ZX296718 PCBOX Board";
14*4882a593Smuzhiyun	compatible = "zte,zx296718-pcbox", "zte,zx296718";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	chosen {
17*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	memory@80000000 {
21*4882a593Smuzhiyun		device_type = "memory";
22*4882a593Smuzhiyun		reg = <0x80000000 0x80000000>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	a53_vdd0v9: regulator-a53 {
26*4882a593Smuzhiyun		compatible = "pwm-regulator";
27*4882a593Smuzhiyun		pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>;
28*4882a593Smuzhiyun		regulator-name = "A53_VDD0V9";
29*4882a593Smuzhiyun		regulator-min-microvolt = <855000>;
30*4882a593Smuzhiyun		regulator-max-microvolt = <1183000>;
31*4882a593Smuzhiyun		pwm-dutycycle-unit = <100>;
32*4882a593Smuzhiyun		pwm-dutycycle-range = <0 100>;
33*4882a593Smuzhiyun		regulator-always-on;
34*4882a593Smuzhiyun		regulator-boot-on;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	sound-spdif0 {
38*4882a593Smuzhiyun		compatible = "audio-graph-card";
39*4882a593Smuzhiyun		dais = <&spdif0_port>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	sound-i2s0 {
43*4882a593Smuzhiyun		compatible = "audio-graph-card";
44*4882a593Smuzhiyun		dais = <&i2s0_port>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun&aud96p22 {
49*4882a593Smuzhiyun	port {
50*4882a593Smuzhiyun		aud96p22_endpoint: endpoint {
51*4882a593Smuzhiyun			remote-endpoint = <&i2s0_endpoint>;
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun&cpu0 {
57*4882a593Smuzhiyun	cpu-supply = <&a53_vdd0v9>;
58*4882a593Smuzhiyun};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun&emmc {
61*4882a593Smuzhiyun	status = "okay";
62*4882a593Smuzhiyun};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun&hdmi {
65*4882a593Smuzhiyun	status = "disabled";
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	port {
68*4882a593Smuzhiyun		hdmi_endpoint: endpoint {
69*4882a593Smuzhiyun			remote-endpoint = <&spdif0_endpoint>;
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&i2c0 {
75*4882a593Smuzhiyun	status = "okay";
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&i2s0 {
79*4882a593Smuzhiyun	status = "okay";
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	i2s0_port: port {
82*4882a593Smuzhiyun		i2s0_endpoint: endpoint {
83*4882a593Smuzhiyun			remote-endpoint = <&aud96p22_endpoint>;
84*4882a593Smuzhiyun			dai-format = "i2s";
85*4882a593Smuzhiyun			frame-master;
86*4882a593Smuzhiyun			bitclock-master;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun&irdec {
92*4882a593Smuzhiyun	status = "okay";
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun&pmm {
96*4882a593Smuzhiyun	pwm3_pins: pwm3 {
97*4882a593Smuzhiyun		pins = "KEY_ROW2";
98*4882a593Smuzhiyun		function = "PWM";
99*4882a593Smuzhiyun	};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun	vga_pins: vga {
102*4882a593Smuzhiyun		pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS";
103*4882a593Smuzhiyun		function = "VGA";
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun&pwm {
108*4882a593Smuzhiyun	pinctrl-names = "default";
109*4882a593Smuzhiyun	pinctrl-0 = <&pwm3_pins>;
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun&sd0 {
114*4882a593Smuzhiyun	status = "okay";
115*4882a593Smuzhiyun};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun&sd1 {
118*4882a593Smuzhiyun	status = "okay";
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&spdif0 {
122*4882a593Smuzhiyun	status = "okay";
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	spdif0_port: port {
125*4882a593Smuzhiyun		spdif0_endpoint: endpoint {
126*4882a593Smuzhiyun			remote-endpoint = <&hdmi_endpoint>;
127*4882a593Smuzhiyun		};
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&tvenc {
132*4882a593Smuzhiyun	status = "disabled";
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&uart0 {
136*4882a593Smuzhiyun	status = "okay";
137*4882a593Smuzhiyun};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun&vga {
140*4882a593Smuzhiyun	pinctrl-names = "default";
141*4882a593Smuzhiyun	pinctrl-0 = <&vga_pins>;
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun};
144