xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * dts file for Xilinx ZynqMP ZCU102 Rev1.0
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2016 - 2018, Xilinx, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun#include "zynqmp-zcu102-revB.dts"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "ZynqMP ZCU102 Rev1.0";
14*4882a593Smuzhiyun	compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
15*4882a593Smuzhiyun};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun&eeprom {
18*4882a593Smuzhiyun	#address-cells = <1>;
19*4882a593Smuzhiyun	#size-cells = <1>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	board_sn: board-sn@0 {
22*4882a593Smuzhiyun		reg = <0x0 0x14>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	eth_mac: eth-mac@20 {
26*4882a593Smuzhiyun		reg = <0x20 0x6>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	board_name: board-name@d0 {
30*4882a593Smuzhiyun		reg = <0xd0 0x6>;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	board_revision: board-revision@e0 {
34*4882a593Smuzhiyun		reg = <0xe0 0x3>;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun};
37