xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * dts file for Xilinx ZynqMP ZC1254
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2015 - 2019, Xilinx, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
8*4882a593Smuzhiyun * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/dts-v1/;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun#include "zynqmp.dtsi"
14*4882a593Smuzhiyun#include "zynqmp-clk-ccf.dtsi"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	model = "ZynqMP ZC1254 RevA";
18*4882a593Smuzhiyun	compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		serial0 = &uart0;
22*4882a593Smuzhiyun		serial1 = &dcc;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	chosen {
26*4882a593Smuzhiyun		bootargs = "earlycon";
27*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	memory@0 {
31*4882a593Smuzhiyun		device_type = "memory";
32*4882a593Smuzhiyun		reg = <0x0 0x0 0x0 0x80000000>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun&dcc {
37*4882a593Smuzhiyun	status = "okay";
38*4882a593Smuzhiyun};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun&uart0 {
41*4882a593Smuzhiyun	status = "okay";
42*4882a593Smuzhiyun};
43