xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/k3-am654-base-board.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "k3-am654.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun#include <dt-bindings/net/ti-dp83867.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	compatible =  "ti,am654-evm", "ti,am654";
14*4882a593Smuzhiyun	model = "Texas Instruments AM654 Base Board";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	chosen {
17*4882a593Smuzhiyun		stdout-path = "serial2:115200n8";
18*4882a593Smuzhiyun		bootargs = "earlycon=ns16550a,mmio32,0x02800000";
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	memory@80000000 {
22*4882a593Smuzhiyun		device_type = "memory";
23*4882a593Smuzhiyun		/* 4G RAM */
24*4882a593Smuzhiyun		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
25*4882a593Smuzhiyun		      <0x00000008 0x80000000 0x00000000 0x80000000>;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	reserved-memory {
29*4882a593Smuzhiyun		#address-cells = <2>;
30*4882a593Smuzhiyun		#size-cells = <2>;
31*4882a593Smuzhiyun		ranges;
32*4882a593Smuzhiyun		secure_ddr: secure-ddr@9e800000 {
33*4882a593Smuzhiyun			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
34*4882a593Smuzhiyun			alignment = <0x1000>;
35*4882a593Smuzhiyun			no-map;
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	gpio-keys {
40*4882a593Smuzhiyun		compatible = "gpio-keys";
41*4882a593Smuzhiyun		autorepeat;
42*4882a593Smuzhiyun		pinctrl-names = "default";
43*4882a593Smuzhiyun		pinctrl-0 = <&push_button_pins_default>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		sw5 {
46*4882a593Smuzhiyun			label = "GPIO Key USER1";
47*4882a593Smuzhiyun			linux,code = <BTN_0>;
48*4882a593Smuzhiyun			gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		sw6 {
52*4882a593Smuzhiyun			label = "GPIO Key USER2";
53*4882a593Smuzhiyun			linux,code = <BTN_1>;
54*4882a593Smuzhiyun			gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	clk_ov5640_fixed: clock {
59*4882a593Smuzhiyun		compatible = "fixed-clock";
60*4882a593Smuzhiyun		#clock-cells = <0>;
61*4882a593Smuzhiyun		clock-frequency = <24000000>;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&wkup_pmx0 {
66*4882a593Smuzhiyun	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
67*4882a593Smuzhiyun		pinctrl-single,pins = <
68*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
69*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
70*4882a593Smuzhiyun		>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	push_button_pins_default: push-button-pins-default {
74*4882a593Smuzhiyun		pinctrl-single,pins = <
75*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
76*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
77*4882a593Smuzhiyun		>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
81*4882a593Smuzhiyun		pinctrl-single,pins = <
82*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
83*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)	 /* (U2) MCU_OSPI0_DQS */
84*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
85*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
86*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
87*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
88*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
89*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
90*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
91*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
92*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
93*4882a593Smuzhiyun		>;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	wkup_pca554_default: wkup-pca554-default {
97*4882a593Smuzhiyun		pinctrl-single,pins = <
98*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
99*4882a593Smuzhiyun		>;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
103*4882a593Smuzhiyun		pinctrl-single,pins = <
104*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
105*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
106*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
107*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
108*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
109*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
110*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
111*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
112*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
113*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
114*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
115*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
116*4882a593Smuzhiyun		>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	mcu_mdio_pins_default: mcu-mdio1-pins-default {
120*4882a593Smuzhiyun		pinctrl-single,pins = <
121*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
122*4882a593Smuzhiyun			AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
123*4882a593Smuzhiyun		>;
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&main_pmx0 {
128*4882a593Smuzhiyun	main_uart0_pins_default: main-uart0-pins-default {
129*4882a593Smuzhiyun		pinctrl-single,pins = <
130*4882a593Smuzhiyun			AM65X_IOPAD(0x01e4, PIN_INPUT, 0)	/* (AF11) UART0_RXD */
131*4882a593Smuzhiyun			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)	/* (AE11) UART0_TXD */
132*4882a593Smuzhiyun			AM65X_IOPAD(0x01ec, PIN_INPUT, 0)	/* (AG11) UART0_CTSn */
133*4882a593Smuzhiyun			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)	/* (AD11) UART0_RTSn */
134*4882a593Smuzhiyun		>;
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	main_i2c2_pins_default: main-i2c2-pins-default {
138*4882a593Smuzhiyun		pinctrl-single,pins = <
139*4882a593Smuzhiyun			AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
140*4882a593Smuzhiyun			AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
141*4882a593Smuzhiyun		>;
142*4882a593Smuzhiyun	};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun	main_spi0_pins_default: main-spi0-pins-default {
145*4882a593Smuzhiyun		pinctrl-single,pins = <
146*4882a593Smuzhiyun			AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
147*4882a593Smuzhiyun			AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
148*4882a593Smuzhiyun			AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
149*4882a593Smuzhiyun			AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
150*4882a593Smuzhiyun		>;
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun	main_mmc0_pins_default: main-mmc0-pins-default {
154*4882a593Smuzhiyun		pinctrl-single,pins = <
155*4882a593Smuzhiyun			AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
156*4882a593Smuzhiyun			AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
157*4882a593Smuzhiyun			AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
158*4882a593Smuzhiyun			AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
159*4882a593Smuzhiyun			AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
160*4882a593Smuzhiyun			AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
161*4882a593Smuzhiyun			AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
162*4882a593Smuzhiyun			AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
163*4882a593Smuzhiyun			AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
164*4882a593Smuzhiyun			AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
165*4882a593Smuzhiyun			AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
166*4882a593Smuzhiyun			AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
167*4882a593Smuzhiyun		>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun	main_mmc1_pins_default: main-mmc1-pins-default {
171*4882a593Smuzhiyun		pinctrl-single,pins = <
172*4882a593Smuzhiyun			AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
173*4882a593Smuzhiyun			AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
174*4882a593Smuzhiyun			AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
175*4882a593Smuzhiyun			AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
176*4882a593Smuzhiyun			AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
177*4882a593Smuzhiyun			AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
178*4882a593Smuzhiyun			AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
179*4882a593Smuzhiyun			AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
180*4882a593Smuzhiyun		>;
181*4882a593Smuzhiyun	};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun	usb1_pins_default: usb1-pins-default {
184*4882a593Smuzhiyun		pinctrl-single,pins = <
185*4882a593Smuzhiyun			AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
186*4882a593Smuzhiyun		>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&main_pmx1 {
191*4882a593Smuzhiyun	main_i2c0_pins_default: main-i2c0-pins-default {
192*4882a593Smuzhiyun		pinctrl-single,pins = <
193*4882a593Smuzhiyun			AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
194*4882a593Smuzhiyun			AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
195*4882a593Smuzhiyun		>;
196*4882a593Smuzhiyun	};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	main_i2c1_pins_default: main-i2c1-pins-default {
199*4882a593Smuzhiyun		pinctrl-single,pins = <
200*4882a593Smuzhiyun			AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
201*4882a593Smuzhiyun			AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
202*4882a593Smuzhiyun		>;
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	ecap0_pins_default: ecap0-pins-default {
206*4882a593Smuzhiyun		pinctrl-single,pins = <
207*4882a593Smuzhiyun			AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
208*4882a593Smuzhiyun		>;
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&wkup_uart0 {
213*4882a593Smuzhiyun	/* Wakeup UART is used by System firmware */
214*4882a593Smuzhiyun	status = "disabled";
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&main_uart0 {
218*4882a593Smuzhiyun	pinctrl-names = "default";
219*4882a593Smuzhiyun	pinctrl-0 = <&main_uart0_pins_default>;
220*4882a593Smuzhiyun	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
221*4882a593Smuzhiyun};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun&wkup_i2c0 {
224*4882a593Smuzhiyun	pinctrl-names = "default";
225*4882a593Smuzhiyun	pinctrl-0 = <&wkup_i2c0_pins_default>;
226*4882a593Smuzhiyun	clock-frequency = <400000>;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun	pca9554: gpio@39 {
229*4882a593Smuzhiyun		compatible = "nxp,pca9554";
230*4882a593Smuzhiyun		reg = <0x39>;
231*4882a593Smuzhiyun		gpio-controller;
232*4882a593Smuzhiyun		#gpio-cells = <2>;
233*4882a593Smuzhiyun		pinctrl-names = "default";
234*4882a593Smuzhiyun		pinctrl-0 = <&wkup_pca554_default>;
235*4882a593Smuzhiyun		interrupt-parent = <&wkup_gpio0>;
236*4882a593Smuzhiyun		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
237*4882a593Smuzhiyun		interrupt-controller;
238*4882a593Smuzhiyun		#interrupt-cells = <2>;
239*4882a593Smuzhiyun	};
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&main_i2c0 {
243*4882a593Smuzhiyun	pinctrl-names = "default";
244*4882a593Smuzhiyun	pinctrl-0 = <&main_i2c0_pins_default>;
245*4882a593Smuzhiyun	clock-frequency = <400000>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun	pca9555: gpio@21 {
248*4882a593Smuzhiyun		compatible = "nxp,pca9555";
249*4882a593Smuzhiyun		reg = <0x21>;
250*4882a593Smuzhiyun		gpio-controller;
251*4882a593Smuzhiyun		#gpio-cells = <2>;
252*4882a593Smuzhiyun	};
253*4882a593Smuzhiyun};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun&main_i2c1 {
256*4882a593Smuzhiyun	pinctrl-names = "default";
257*4882a593Smuzhiyun	pinctrl-0 = <&main_i2c1_pins_default>;
258*4882a593Smuzhiyun	clock-frequency = <400000>;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	ov5640: camera@3c {
261*4882a593Smuzhiyun		compatible = "ovti,ov5640";
262*4882a593Smuzhiyun		reg = <0x3c>;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun		clocks = <&clk_ov5640_fixed>;
265*4882a593Smuzhiyun		clock-names = "xclk";
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun		port {
268*4882a593Smuzhiyun			csi2_cam0: endpoint {
269*4882a593Smuzhiyun				remote-endpoint = <&csi2_phy0>;
270*4882a593Smuzhiyun				clock-lanes = <0>;
271*4882a593Smuzhiyun				data-lanes = <1 2>;
272*4882a593Smuzhiyun			};
273*4882a593Smuzhiyun		};
274*4882a593Smuzhiyun	};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun&main_i2c2 {
279*4882a593Smuzhiyun	pinctrl-names = "default";
280*4882a593Smuzhiyun	pinctrl-0 = <&main_i2c2_pins_default>;
281*4882a593Smuzhiyun	clock-frequency = <400000>;
282*4882a593Smuzhiyun};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun&ecap0 {
285*4882a593Smuzhiyun	pinctrl-names = "default";
286*4882a593Smuzhiyun	pinctrl-0 = <&ecap0_pins_default>;
287*4882a593Smuzhiyun};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun&main_spi0 {
290*4882a593Smuzhiyun	pinctrl-names = "default";
291*4882a593Smuzhiyun	pinctrl-0 = <&main_spi0_pins_default>;
292*4882a593Smuzhiyun	#address-cells = <1>;
293*4882a593Smuzhiyun	#size-cells= <0>;
294*4882a593Smuzhiyun	ti,pindir-d0-out-d1-in = <1>;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	flash@0{
297*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
298*4882a593Smuzhiyun		reg = <0x0>;
299*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
300*4882a593Smuzhiyun		spi-rx-bus-width = <1>;
301*4882a593Smuzhiyun		spi-max-frequency = <48000000>;
302*4882a593Smuzhiyun		#address-cells = <1>;
303*4882a593Smuzhiyun		#size-cells= <1>;
304*4882a593Smuzhiyun	};
305*4882a593Smuzhiyun};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun&sdhci0 {
308*4882a593Smuzhiyun	pinctrl-names = "default";
309*4882a593Smuzhiyun	pinctrl-0 = <&main_mmc0_pins_default>;
310*4882a593Smuzhiyun	bus-width = <8>;
311*4882a593Smuzhiyun	non-removable;
312*4882a593Smuzhiyun	ti,driver-strength-ohm = <50>;
313*4882a593Smuzhiyun	disable-wp;
314*4882a593Smuzhiyun};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun/*
317*4882a593Smuzhiyun * Because of erratas i2025 and i2026 for silicon revision 1.0, the
318*4882a593Smuzhiyun * SD card interface might fail. Boards with sr1.0 are recommended to
319*4882a593Smuzhiyun * disable sdhci1
320*4882a593Smuzhiyun */
321*4882a593Smuzhiyun&sdhci1 {
322*4882a593Smuzhiyun	pinctrl-names = "default";
323*4882a593Smuzhiyun	pinctrl-0 = <&main_mmc1_pins_default>;
324*4882a593Smuzhiyun	ti,driver-strength-ohm = <50>;
325*4882a593Smuzhiyun	disable-wp;
326*4882a593Smuzhiyun};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun&dwc3_1 {
329*4882a593Smuzhiyun	status = "okay";
330*4882a593Smuzhiyun};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun&usb1_phy {
333*4882a593Smuzhiyun	status = "okay";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&usb1 {
337*4882a593Smuzhiyun	pinctrl-names = "default";
338*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins_default>;
339*4882a593Smuzhiyun	dr_mode = "otg";
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&dwc3_0 {
343*4882a593Smuzhiyun	status = "disabled";
344*4882a593Smuzhiyun};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun&usb0_phy {
347*4882a593Smuzhiyun	status = "disabled";
348*4882a593Smuzhiyun};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun&tscadc0 {
351*4882a593Smuzhiyun	adc {
352*4882a593Smuzhiyun		ti,adc-channels = <0 1 2 3 4 5 6 7>;
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&tscadc1 {
357*4882a593Smuzhiyun	adc {
358*4882a593Smuzhiyun		ti,adc-channels = <0 1 2 3 4 5 6 7>;
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun&serdes0 {
363*4882a593Smuzhiyun	status = "disabled";
364*4882a593Smuzhiyun};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun&serdes1 {
367*4882a593Smuzhiyun	status = "disabled";
368*4882a593Smuzhiyun};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun&pcie0_rc {
371*4882a593Smuzhiyun	status = "disabled";
372*4882a593Smuzhiyun};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun&pcie0_ep {
375*4882a593Smuzhiyun	status = "disabled";
376*4882a593Smuzhiyun};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun&pcie1_rc {
379*4882a593Smuzhiyun	status = "disabled";
380*4882a593Smuzhiyun};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun&pcie1_ep {
383*4882a593Smuzhiyun	status = "disabled";
384*4882a593Smuzhiyun};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun&mailbox0_cluster0 {
387*4882a593Smuzhiyun	interrupts = <436>;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
390*4882a593Smuzhiyun		ti,mbox-tx = <1 0 0>;
391*4882a593Smuzhiyun		ti,mbox-rx = <0 0 0>;
392*4882a593Smuzhiyun	};
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&mailbox0_cluster1 {
396*4882a593Smuzhiyun	interrupts = <432>;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
399*4882a593Smuzhiyun		ti,mbox-tx = <1 0 0>;
400*4882a593Smuzhiyun		ti,mbox-rx = <0 0 0>;
401*4882a593Smuzhiyun	};
402*4882a593Smuzhiyun};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun&mailbox0_cluster2 {
405*4882a593Smuzhiyun	status = "disabled";
406*4882a593Smuzhiyun};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun&mailbox0_cluster3 {
409*4882a593Smuzhiyun	status = "disabled";
410*4882a593Smuzhiyun};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun&mailbox0_cluster4 {
413*4882a593Smuzhiyun	status = "disabled";
414*4882a593Smuzhiyun};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun&mailbox0_cluster5 {
417*4882a593Smuzhiyun	status = "disabled";
418*4882a593Smuzhiyun};
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun&mailbox0_cluster6 {
421*4882a593Smuzhiyun	status = "disabled";
422*4882a593Smuzhiyun};
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun&mailbox0_cluster7 {
425*4882a593Smuzhiyun	status = "disabled";
426*4882a593Smuzhiyun};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun&mailbox0_cluster8 {
429*4882a593Smuzhiyun	status = "disabled";
430*4882a593Smuzhiyun};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun&mailbox0_cluster9 {
433*4882a593Smuzhiyun	status = "disabled";
434*4882a593Smuzhiyun};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun&mailbox0_cluster10 {
437*4882a593Smuzhiyun	status = "disabled";
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&mailbox0_cluster11 {
441*4882a593Smuzhiyun	status = "disabled";
442*4882a593Smuzhiyun};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun&ospi0 {
445*4882a593Smuzhiyun	pinctrl-names = "default";
446*4882a593Smuzhiyun	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	flash@0{
449*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
450*4882a593Smuzhiyun		reg = <0x0>;
451*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
452*4882a593Smuzhiyun		spi-rx-bus-width = <8>;
453*4882a593Smuzhiyun		spi-max-frequency = <40000000>;
454*4882a593Smuzhiyun		cdns,tshsl-ns = <60>;
455*4882a593Smuzhiyun		cdns,tsd2d-ns = <60>;
456*4882a593Smuzhiyun		cdns,tchsh-ns = <60>;
457*4882a593Smuzhiyun		cdns,tslch-ns = <60>;
458*4882a593Smuzhiyun		cdns,read-delay = <0>;
459*4882a593Smuzhiyun		#address-cells = <1>;
460*4882a593Smuzhiyun		#size-cells = <1>;
461*4882a593Smuzhiyun	};
462*4882a593Smuzhiyun};
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun&csi2_0 {
465*4882a593Smuzhiyun	csi2_phy0: endpoint {
466*4882a593Smuzhiyun		remote-endpoint = <&csi2_cam0>;
467*4882a593Smuzhiyun		clock-lanes = <0>;
468*4882a593Smuzhiyun		data-lanes = <1 2>;
469*4882a593Smuzhiyun	};
470*4882a593Smuzhiyun};
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun&mcu_cpsw {
473*4882a593Smuzhiyun	pinctrl-names = "default";
474*4882a593Smuzhiyun	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
475*4882a593Smuzhiyun};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun&davinci_mdio {
478*4882a593Smuzhiyun	phy0: ethernet-phy@0 {
479*4882a593Smuzhiyun		reg = <0>;
480*4882a593Smuzhiyun		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
481*4882a593Smuzhiyun		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
482*4882a593Smuzhiyun	};
483*4882a593Smuzhiyun};
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun&cpsw_port1 {
486*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
487*4882a593Smuzhiyun	phy-handle = <&phy0>;
488*4882a593Smuzhiyun};
489