xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Device Tree Source for UniPhier PXs3 Reference Board
4*4882a593Smuzhiyun//
5*4882a593Smuzhiyun// Copyright (C) 2017 Socionext Inc.
6*4882a593Smuzhiyun//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun#include "uniphier-pxs3.dtsi"
10*4882a593Smuzhiyun#include "uniphier-support-card.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "UniPhier PXs3 Reference Board";
14*4882a593Smuzhiyun	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	chosen {
17*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		serial0 = &serial0;
22*4882a593Smuzhiyun		serial1 = &serialsc;
23*4882a593Smuzhiyun		serial2 = &serial2;
24*4882a593Smuzhiyun		serial3 = &serial3;
25*4882a593Smuzhiyun		i2c0 = &i2c0;
26*4882a593Smuzhiyun		i2c1 = &i2c1;
27*4882a593Smuzhiyun		i2c2 = &i2c2;
28*4882a593Smuzhiyun		i2c3 = &i2c3;
29*4882a593Smuzhiyun		i2c6 = &i2c6;
30*4882a593Smuzhiyun		spi0 = &spi0;
31*4882a593Smuzhiyun		spi1 = &spi1;
32*4882a593Smuzhiyun		ethernet0 = &eth0;
33*4882a593Smuzhiyun		ethernet1 = &eth1;
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	memory@80000000 {
37*4882a593Smuzhiyun		device_type = "memory";
38*4882a593Smuzhiyun		reg = <0 0x80000000 0 0xa0000000>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun&ethsc {
43*4882a593Smuzhiyun	interrupts = <4 8>;
44*4882a593Smuzhiyun};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun&serialsc {
47*4882a593Smuzhiyun	interrupts = <4 8>;
48*4882a593Smuzhiyun};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun&spi0 {
51*4882a593Smuzhiyun	status = "okay";
52*4882a593Smuzhiyun};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun&spi1 {
55*4882a593Smuzhiyun	status = "okay";
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&serial0 {
59*4882a593Smuzhiyun	status = "okay";
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&serial2 {
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&serial3 {
67*4882a593Smuzhiyun	status = "okay";
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&gpio {
71*4882a593Smuzhiyun	xirq4 {
72*4882a593Smuzhiyun		gpio-hog;
73*4882a593Smuzhiyun		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
74*4882a593Smuzhiyun		input;
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&i2c0 {
79*4882a593Smuzhiyun	status = "okay";
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&i2c1 {
83*4882a593Smuzhiyun	status = "okay";
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&i2c2 {
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&i2c3 {
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun&sd {
95*4882a593Smuzhiyun	status = "okay";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&eth0 {
99*4882a593Smuzhiyun	status = "okay";
100*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
101*4882a593Smuzhiyun};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun&mdio0 {
104*4882a593Smuzhiyun	ethphy0: ethernet-phy@0 {
105*4882a593Smuzhiyun		reg = <0>;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&eth1 {
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun	phy-handle = <&ethphy1>;
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&mdio1 {
115*4882a593Smuzhiyun	ethphy1: ethernet-phy@0 {
116*4882a593Smuzhiyun		reg = <0>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun&usb0 {
121*4882a593Smuzhiyun	status = "okay";
122*4882a593Smuzhiyun};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun&usb1 {
125*4882a593Smuzhiyun	status = "okay";
126*4882a593Smuzhiyun};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun&pcie {
129*4882a593Smuzhiyun	status = "okay";
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&nand {
133*4882a593Smuzhiyun	status = "okay";
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	nand@0 {
136*4882a593Smuzhiyun		reg = <0>;
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&pinctrl_ether_rgmii {
141*4882a593Smuzhiyun	tx {
142*4882a593Smuzhiyun		pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
143*4882a593Smuzhiyun		       "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
144*4882a593Smuzhiyun		drive-strength = <9>;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&pinctrl_ether1_rgmii {
149*4882a593Smuzhiyun	tx {
150*4882a593Smuzhiyun		pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
151*4882a593Smuzhiyun		       "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
152*4882a593Smuzhiyun		drive-strength = <9>;
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun};
155