xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/usb/pd.h>
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
12*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
13*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h>
14*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
15*4882a593Smuzhiyun#include "rk3588s.dtsi"
16*4882a593Smuzhiyun#include "rk3588-android.dtsi"
17*4882a593Smuzhiyun#include "rk3588s-rk806-dual.dtsi"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/ {
20*4882a593Smuzhiyun	adc_keys: adc-keys {
21*4882a593Smuzhiyun		compatible = "adc-keys";
22*4882a593Smuzhiyun		io-channels = <&saradc 1>;
23*4882a593Smuzhiyun		io-channel-names = "buttons";
24*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
25*4882a593Smuzhiyun		poll-interval = <100>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		vol-up-key {
28*4882a593Smuzhiyun			label = "volume up";
29*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
30*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		vol-down-key {
34*4882a593Smuzhiyun			label = "volume down";
35*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
36*4882a593Smuzhiyun			press-threshold-microvolt = <417000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	backlight: backlight {
41*4882a593Smuzhiyun		compatible = "pwm-backlight";
42*4882a593Smuzhiyun		pwms = <&pwm12 0 25000 0>;
43*4882a593Smuzhiyun		brightness-levels = <
44*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
45*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
46*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
47*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
48*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
49*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
50*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
51*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
52*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
53*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
54*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
55*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
56*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
57*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
58*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
59*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
60*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
61*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
62*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
63*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
64*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
65*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
66*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
67*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
68*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
69*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
70*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
71*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
72*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
73*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
74*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
75*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
76*4882a593Smuzhiyun		>;
77*4882a593Smuzhiyun		default-brightness-level = <200>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	battery: battery {
81*4882a593Smuzhiyun		compatible = "simple-battery";
82*4882a593Smuzhiyun		charge-full-design-microamp-hours = <4500000>;
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	bt_sco: bt-sco {
86*4882a593Smuzhiyun		status = "disabled";
87*4882a593Smuzhiyun		compatible = "delta,dfbmcs320";
88*4882a593Smuzhiyun		#sound-dai-cells = <1>;
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	bt_sound: bt-sound {
92*4882a593Smuzhiyun		status = "disabled";
93*4882a593Smuzhiyun		compatible = "simple-audio-card";
94*4882a593Smuzhiyun		simple-audio-card,format = "dsp_a";
95*4882a593Smuzhiyun		simple-audio-card,bitclock-inversion = <0>;
96*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
97*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,bt";
98*4882a593Smuzhiyun		simple-audio-card,cpu {
99*4882a593Smuzhiyun			sound-dai = <&i2s2_2ch>;
100*4882a593Smuzhiyun		};
101*4882a593Smuzhiyun		simple-audio-card,codec {
102*4882a593Smuzhiyun			sound-dai = <&bt_sco 1>;
103*4882a593Smuzhiyun		};
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	charge-animation {
107*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
108*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
109*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
110*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <6800>;
111*4882a593Smuzhiyun		rockchip,screen-on-voltage = <6900>;
112*4882a593Smuzhiyun		rockchip,uboot-exit-charge-level = <2>;
113*4882a593Smuzhiyun		rockchip,uboot-exit-charge-auto = <0>;
114*4882a593Smuzhiyun		rockchip,system-suspend = <1>;
115*4882a593Smuzhiyun		regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>,
116*4882a593Smuzhiyun		      <&vdd2_ddr_s3>, <&vcc_1v1_nldo_s3>,
117*4882a593Smuzhiyun		      <&vdd1_1v8_ddr_s3>, <&vcc_1v8_s3>,
118*4882a593Smuzhiyun		      <&master_pldo6_s3>, <&vdd_0v75_s3>,
119*4882a593Smuzhiyun		      <&vdd2l_0v9_ddr_s3>, <&vdd_1v8_pll_s0>, <&pldo6_s3>;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>,
122*4882a593Smuzhiyun		       <&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>,
123*4882a593Smuzhiyun		       <&vdd_vdenc_mem_s0>, <&avcc_1v8_s0>, <&vcc_3v3_s0>,
124*4882a593Smuzhiyun		       <&vccio_sd_s0>, <&master_nldo3>, <&avdd_0v75_s0>,
125*4882a593Smuzhiyun		       <&vdd_0v85_s0>, <&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>,
126*4882a593Smuzhiyun		       <&vdd_cpu_lit_s0>, <&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>,
127*4882a593Smuzhiyun		       <&vcc_1v8_s0>, <&vdd_cpu_lit_mem_s0>, <&vddq_ddr_s0>,
128*4882a593Smuzhiyun		       <&vdd_ddr_s0>, <&vcc_1v8_cam_s0>, <&avdd1v8_ddr_pll_s0>,
129*4882a593Smuzhiyun		       <&vcc_3v3_sd_s0>, <&vcc_2v8_cam_s0>, <&vdd_0v75_pll_s0>,
130*4882a593Smuzhiyun		       <&vdd_ddr_pll_s0>, <&slave_nldo3>, <&avdd_1v2_cam_s0>,
131*4882a593Smuzhiyun		       <&avdd_1v2_s0>, <&vcc_3v3_s3>;
132*4882a593Smuzhiyun		status = "okay";
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	dp0_sound: dp0-sound {
136*4882a593Smuzhiyun		status = "okay";
137*4882a593Smuzhiyun		compatible = "rockchip,hdmi";
138*4882a593Smuzhiyun		rockchip,card-name= "rockchip-dp0";
139*4882a593Smuzhiyun		rockchip,mclk-fs = <512>;
140*4882a593Smuzhiyun		rockchip,cpu = <&spdif_tx2>;
141*4882a593Smuzhiyun		rockchip,codec = <&dp0 1>;
142*4882a593Smuzhiyun		rockchip,jack-det;
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun	es7202_sound_micarray: es7202-sound-micarray {
146*4882a593Smuzhiyun		status = "okay";
147*4882a593Smuzhiyun		compatible = "simple-audio-card";
148*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
149*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,sound-micarray";
150*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
151*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
152*4882a593Smuzhiyun			format = "pdm";
153*4882a593Smuzhiyun			cpu {
154*4882a593Smuzhiyun				sound-dai = <&pdm0>;
155*4882a593Smuzhiyun			};
156*4882a593Smuzhiyun			codec {
157*4882a593Smuzhiyun				sound-dai = <&es7202>;
158*4882a593Smuzhiyun			};
159*4882a593Smuzhiyun		};
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	es8388_sound: es8388-sound {
163*4882a593Smuzhiyun		status = "okay";
164*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
165*4882a593Smuzhiyun		rockchip,card-name = "rockchip,es8388-codec";
166*4882a593Smuzhiyun		hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
167*4882a593Smuzhiyun		io-channels = <&saradc 3>;
168*4882a593Smuzhiyun		io-channel-names = "adc-detect";
169*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
170*4882a593Smuzhiyun		poll-interval = <100>;
171*4882a593Smuzhiyun		spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
172*4882a593Smuzhiyun		hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
173*4882a593Smuzhiyun		rockchip,format = "i2s";
174*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
175*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
176*4882a593Smuzhiyun		rockchip,codec = <&es8388>;
177*4882a593Smuzhiyun		rockchip,audio-routing =
178*4882a593Smuzhiyun			"Headphone", "LOUT1",
179*4882a593Smuzhiyun			"Headphone", "ROUT1",
180*4882a593Smuzhiyun			"Speaker", "LOUT2",
181*4882a593Smuzhiyun			"Speaker", "ROUT2",
182*4882a593Smuzhiyun			"Headphone", "Headphone Power",
183*4882a593Smuzhiyun			"Headphone", "Headphone Power",
184*4882a593Smuzhiyun			"Speaker", "Speaker Power",
185*4882a593Smuzhiyun			"Speaker", "Speaker Power",
186*4882a593Smuzhiyun			"LINPUT1", "Main Mic",
187*4882a593Smuzhiyun			"LINPUT2", "Main Mic",
188*4882a593Smuzhiyun			"RINPUT1", "Headset Mic",
189*4882a593Smuzhiyun			"RINPUT2", "Headset Mic";
190*4882a593Smuzhiyun		pinctrl-names = "default";
191*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
192*4882a593Smuzhiyun		play-pause-key {
193*4882a593Smuzhiyun			label = "playpause";
194*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
195*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
196*4882a593Smuzhiyun		};
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun	hall_sensor: hall-mh248 {
200*4882a593Smuzhiyun		compatible = "hall-mh248";
201*4882a593Smuzhiyun		pinctrl-names = "default";
202*4882a593Smuzhiyun		pinctrl-0 = <&mh248_irq_gpio>;
203*4882a593Smuzhiyun		irq-gpio = <&gpio1 RK_PA1 IRQ_TYPE_EDGE_BOTH>;
204*4882a593Smuzhiyun		hall-active = <1>;
205*4882a593Smuzhiyun		status = "okay";
206*4882a593Smuzhiyun	};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	panel-edp {
209*4882a593Smuzhiyun		compatible = "innolux,p120zdg-bf4", "simple-panel";
210*4882a593Smuzhiyun		backlight = <&backlight>;
211*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_edp>;
212*4882a593Smuzhiyun		prepare-delay-ms = <120>;
213*4882a593Smuzhiyun		enable-delay-ms = <120>;
214*4882a593Smuzhiyun		unprepare-delay-ms = <500>;
215*4882a593Smuzhiyun		disable-delay-ms = <120>;
216*4882a593Smuzhiyun		width-mm = <254>;
217*4882a593Smuzhiyun		height-mm = <169>;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun		panel-timing {
220*4882a593Smuzhiyun			clock-frequency = <206000000>;
221*4882a593Smuzhiyun			hactive = <2160>;
222*4882a593Smuzhiyun			vactive = <1440>;
223*4882a593Smuzhiyun			hfront-porch = <48>;
224*4882a593Smuzhiyun			hsync-len = <32>;
225*4882a593Smuzhiyun			hback-porch = <80>;
226*4882a593Smuzhiyun			vfront-porch = <3>;
227*4882a593Smuzhiyun			vsync-len = <10>;
228*4882a593Smuzhiyun			vback-porch = <27>;
229*4882a593Smuzhiyun			hsync-active = <0>;
230*4882a593Smuzhiyun			vsync-active = <0>;
231*4882a593Smuzhiyun			de-active = <0>;
232*4882a593Smuzhiyun			pixelclk-active = <0>;
233*4882a593Smuzhiyun		};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun		port {
236*4882a593Smuzhiyun			panel_in_edp: endpoint {
237*4882a593Smuzhiyun				remote-endpoint = <&edp0_out>;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun		};
240*4882a593Smuzhiyun	};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	vcc3v3_lcd_edp: vcc3v3-lcd-edp {
243*4882a593Smuzhiyun		compatible = "regulator-fixed";
244*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd_edp";
245*4882a593Smuzhiyun		regulator-boot-on;
246*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
247*4882a593Smuzhiyun		enable-active-high;
248*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
249*4882a593Smuzhiyun	};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
252*4882a593Smuzhiyun		compatible = "regulator-fixed";
253*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
254*4882a593Smuzhiyun		regulator-boot-on;
255*4882a593Smuzhiyun		regulator-always-on;
256*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
257*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
258*4882a593Smuzhiyun		enable-active-high;
259*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
260*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
261*4882a593Smuzhiyun		pinctrl-names = "default";
262*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
266*4882a593Smuzhiyun		compatible = "regulator-fixed";
267*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
268*4882a593Smuzhiyun		regulator-always-on;
269*4882a593Smuzhiyun		regulator-boot-on;
270*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
271*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	vcc5v0_usb: vcc5v0-usb {
275*4882a593Smuzhiyun		compatible = "regulator-fixed";
276*4882a593Smuzhiyun		regulator-name = "vcc5v0_usb";
277*4882a593Smuzhiyun		regulator-always-on;
278*4882a593Smuzhiyun		regulator-boot-on;
279*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
280*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
281*4882a593Smuzhiyun	};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	vcc_mipidcphy1: vcc-mipidcphy1-regulator {
284*4882a593Smuzhiyun		compatible = "regulator-fixed";
285*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
286*4882a593Smuzhiyun		pinctrl-names = "default";
287*4882a593Smuzhiyun		pinctrl-0 = <&mipidcphy1_pwr>;
288*4882a593Smuzhiyun		regulator-name = "vcc_mipidcphy1";
289*4882a593Smuzhiyun		enable-active-high;
290*4882a593Smuzhiyun		regulator-always-on;
291*4882a593Smuzhiyun		regulator-boot-on;
292*4882a593Smuzhiyun	};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
295*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
296*4882a593Smuzhiyun		clocks = <&hym8563>;
297*4882a593Smuzhiyun		clock-names = "ext_clock";
298*4882a593Smuzhiyun		uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
299*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
300*4882a593Smuzhiyun		pinctrl-0 = <&uart7m1_rtsn>,  <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
301*4882a593Smuzhiyun		pinctrl-1 = <&uart7_gpios>;
302*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
303*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
304*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
305*4882a593Smuzhiyun		status = "okay";
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
309*4882a593Smuzhiyun		compatible = "wlan-platdata";
310*4882a593Smuzhiyun		wifi_chip_type = "ap6275p";
311*4882a593Smuzhiyun		pinctrl-names = "default";
312*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
313*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
314*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
315*4882a593Smuzhiyun		status = "okay";
316*4882a593Smuzhiyun	};
317*4882a593Smuzhiyun};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun&av1d_mmu {
320*4882a593Smuzhiyun	status = "okay";
321*4882a593Smuzhiyun};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun&avdd_1v2_cam_s0 {
324*4882a593Smuzhiyun	regulator-min-microvolt = <1350000>;
325*4882a593Smuzhiyun	regulator-max-microvolt = <1350000>;
326*4882a593Smuzhiyun	regulator-ramp-delay = <12500>;
327*4882a593Smuzhiyun};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun&combphy0_ps {
330*4882a593Smuzhiyun	status = "okay";
331*4882a593Smuzhiyun};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun&cpu_l0 {
334*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_lit_s0>;
335*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_lit_mem_s0>;
336*4882a593Smuzhiyun};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun&cpu_b0 {
339*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_big0_s0>;
340*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_big0_mem_s0>;
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&cpu_b2 {
344*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_big1_s0>;
345*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_big1_mem_s0>;
346*4882a593Smuzhiyun};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun&dp0 {
349*4882a593Smuzhiyun	status = "okay";
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&dp0_out {
353*4882a593Smuzhiyun	link-frequencies = /bits/ 64 <5400000000>;
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&dp0_in_vp1 {
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun&edp0 {
361*4882a593Smuzhiyun	support-psr;
362*4882a593Smuzhiyun	force-hpd;
363*4882a593Smuzhiyun	status = "okay";
364*4882a593Smuzhiyun};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun&edp0_in_vp2 {
367*4882a593Smuzhiyun	status = "okay";
368*4882a593Smuzhiyun};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun&edp0_out {
371*4882a593Smuzhiyun	remote-endpoint = <&panel_in_edp>;
372*4882a593Smuzhiyun};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun&fiq_debugger {
375*4882a593Smuzhiyun	pinctrl-0 = <&uart2m1_xfer>;
376*4882a593Smuzhiyun};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun&gpu {
379*4882a593Smuzhiyun	mali-supply = <&vdd_gpu_s0>;
380*4882a593Smuzhiyun	mem-supply = <&vdd_gpu_mem_s0>;
381*4882a593Smuzhiyun	status = "okay";
382*4882a593Smuzhiyun};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun&hdptxphy0 {
385*4882a593Smuzhiyun	/* Single Vdiff Training Table for power reduction (optional) */
386*4882a593Smuzhiyun	training-table = /bits/ 8 <
387*4882a593Smuzhiyun		/* voltage swing 0, pre-emphasis 0->3 */
388*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
389*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
390*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
391*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
392*4882a593Smuzhiyun		/* voltage swing 1, pre-emphasis 0->2 */
393*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
394*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
395*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
396*4882a593Smuzhiyun		/* voltage swing 2, pre-emphasis 0->1 */
397*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
398*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
399*4882a593Smuzhiyun		/* voltage swing 3, pre-emphasis 0 */
400*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
401*4882a593Smuzhiyun	>;
402*4882a593Smuzhiyun	status = "okay";
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&i2c2 {
406*4882a593Smuzhiyun	status = "okay";
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun	hym8563: hym8563@51 {
409*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
410*4882a593Smuzhiyun		reg = <0x51>;
411*4882a593Smuzhiyun		#clock-cells = <0>;
412*4882a593Smuzhiyun		clock-frequency = <32768>;
413*4882a593Smuzhiyun		clock-output-names = "hym8563";
414*4882a593Smuzhiyun		pinctrl-names = "default";
415*4882a593Smuzhiyun		pinctrl-0 = <&rtc_int>;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
418*4882a593Smuzhiyun		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
419*4882a593Smuzhiyun		wakeup-source;
420*4882a593Smuzhiyun	};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun	cw2015@62 {
423*4882a593Smuzhiyun		status = "okay";
424*4882a593Smuzhiyun		compatible = "cellwise,cw2015";
425*4882a593Smuzhiyun		reg = <0x62>;
426*4882a593Smuzhiyun		cellwise,battery-profile = /bits/ 8
427*4882a593Smuzhiyun			<0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B
428*4882a593Smuzhiyun			 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D
429*4882a593Smuzhiyun			 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49
430*4882a593Smuzhiyun			 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49
431*4882a593Smuzhiyun			 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35
432*4882a593Smuzhiyun			 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17
433*4882a593Smuzhiyun			 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB
434*4882a593Smuzhiyun			 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>;
435*4882a593Smuzhiyun		cellwise,dual-cell = <1>;
436*4882a593Smuzhiyun		cellwise,monitor-interval-ms = <5000>;
437*4882a593Smuzhiyun		monitored-battery = <&battery>;
438*4882a593Smuzhiyun		power-supplies = <&bq25703>;
439*4882a593Smuzhiyun	};
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun	bq25703: bq25703@6b {
442*4882a593Smuzhiyun		status = "okay";
443*4882a593Smuzhiyun		compatible = "ti,bq25703";
444*4882a593Smuzhiyun		reg = <0x6b>;
445*4882a593Smuzhiyun		ti,usb-charger-detection = <&usbc0>;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
448*4882a593Smuzhiyun		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
449*4882a593Smuzhiyun		otg-mode-en-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
450*4882a593Smuzhiyun		pinctrl-names = "default";
451*4882a593Smuzhiyun		pinctrl-0 = <&charger_ok>;
452*4882a593Smuzhiyun		extcon = <&u2phy0>;
453*4882a593Smuzhiyun		ti,charge-current = <2500000>;
454*4882a593Smuzhiyun		ti,max-input-voltage = <20000000>;
455*4882a593Smuzhiyun		ti,max-input-current = <6000000>;
456*4882a593Smuzhiyun		ti,max-charge-voltage = <8750000>;
457*4882a593Smuzhiyun		ti,input-current = <500000>;
458*4882a593Smuzhiyun		ti,input-current-sdp = <500000>;
459*4882a593Smuzhiyun		ti,input-current-dcp = <2000000>;
460*4882a593Smuzhiyun		ti,input-current-cdp = <2000000>;
461*4882a593Smuzhiyun		ti,minimum-sys-voltage = <7400000>;
462*4882a593Smuzhiyun		ti,otg-voltage = <5000000>;
463*4882a593Smuzhiyun		ti,otg-current = <1500000>;
464*4882a593Smuzhiyun		pd-charge-only = <0>;
465*4882a593Smuzhiyun		regulators {
466*4882a593Smuzhiyun			vbus5v0_typec: vbus5v0-typec {
467*4882a593Smuzhiyun				regulator-compatible = "otg-vbus";
468*4882a593Smuzhiyun				regulator-name = "vbus5v0_typec";
469*4882a593Smuzhiyun			};
470*4882a593Smuzhiyun		};
471*4882a593Smuzhiyun	};
472*4882a593Smuzhiyun};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun&i2c3 {
475*4882a593Smuzhiyun	status = "okay";
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun	es8388: es8388@11 {
478*4882a593Smuzhiyun		status = "okay";
479*4882a593Smuzhiyun		#sound-dai-cells = <0>;
480*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
481*4882a593Smuzhiyun		reg = <0x11>;
482*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
483*4882a593Smuzhiyun		clock-names = "mclk";
484*4882a593Smuzhiyun		assigned-clocks = <&mclkout_i2s0>;
485*4882a593Smuzhiyun		assigned-clock-rates = <12288000>;
486*4882a593Smuzhiyun		pinctrl-names = "default";
487*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
488*4882a593Smuzhiyun	};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun	es7202: es7202@32 {
491*4882a593Smuzhiyun		status = "okay";
492*4882a593Smuzhiyun		#sound-dai-cells = <0>;
493*4882a593Smuzhiyun		compatible = "ES7202_PDM_ADC_1";
494*4882a593Smuzhiyun		power-supply = <&vcc_1v8_s0>;	/* only 1v8 or 3v3, default is 3v3 */
495*4882a593Smuzhiyun		reg = <0x32>;
496*4882a593Smuzhiyun	};
497*4882a593Smuzhiyun};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun&i2c4 {
500*4882a593Smuzhiyun	status = "okay";
501*4882a593Smuzhiyun	pinctrl-names = "default";
502*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m3_xfer>;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun	elan_touch: elan_ktf@10 {
505*4882a593Smuzhiyun		status = "okay";
506*4882a593Smuzhiyun		compatible = "elan,ektf";
507*4882a593Smuzhiyun		reg = <0x10>;
508*4882a593Smuzhiyun		pinctrl-names = "default";
509*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
510*4882a593Smuzhiyun		elan,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
511*4882a593Smuzhiyun		elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
512*4882a593Smuzhiyun		chip_type = <0x01>;	/* 1:HID IIC, 0: NORMAL IIC */
513*4882a593Smuzhiyun		report_type = <0x01>;	/* 1:B protocol, 0:A protocol */
514*4882a593Smuzhiyun	};
515*4882a593Smuzhiyun};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun&i2c5 {
518*4882a593Smuzhiyun	status = "okay";
519*4882a593Smuzhiyun	pinctrl-names = "default";
520*4882a593Smuzhiyun	pinctrl-0 = <&i2c5m0_xfer>;
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun	mpu6500_acc: mpu_acc@68 {
523*4882a593Smuzhiyun		status = "okay";
524*4882a593Smuzhiyun		compatible = "mpu6500_acc";
525*4882a593Smuzhiyun		reg = <0x68>;
526*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>;
527*4882a593Smuzhiyun		irq_enable = <0>;
528*4882a593Smuzhiyun		poll_delay_ms = <30>;
529*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
530*4882a593Smuzhiyun		layout = <5>;
531*4882a593Smuzhiyun	};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun	mpu6500_gyro: mpu_gyro@68 {
534*4882a593Smuzhiyun		status = "okay";
535*4882a593Smuzhiyun		compatible = "mpu6500_gyro";
536*4882a593Smuzhiyun		reg = <0x68>;
537*4882a593Smuzhiyun		poll_delay_ms = <30>;
538*4882a593Smuzhiyun		type = <SENSOR_TYPE_GYROSCOPE>;
539*4882a593Smuzhiyun		layout = <5>;
540*4882a593Smuzhiyun	};
541*4882a593Smuzhiyun};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun&i2c6 {
544*4882a593Smuzhiyun	status = "disabled";
545*4882a593Smuzhiyun};
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun&i2c7 {
548*4882a593Smuzhiyun	status = "okay";
549*4882a593Smuzhiyun	pinctrl-names = "default";
550*4882a593Smuzhiyun	pinctrl-0 = <&i2c7m2_xfer>;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun	aw8601: aw8601@c {
553*4882a593Smuzhiyun		compatible = "awinic,aw8601";
554*4882a593Smuzhiyun		status = "okay";
555*4882a593Smuzhiyun		reg = <0x0c>;
556*4882a593Smuzhiyun		rockchip,vcm-start-current = <56>;
557*4882a593Smuzhiyun		rockchip,vcm-rated-current = <96>;
558*4882a593Smuzhiyun		rockchip,vcm-step-mode = <4>;
559*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
560*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
561*4882a593Smuzhiyun	};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun	ov13855: ov13855@10 {
564*4882a593Smuzhiyun		compatible = "ovti,ov13855";
565*4882a593Smuzhiyun		status = "okay";
566*4882a593Smuzhiyun		reg = <0x10>;
567*4882a593Smuzhiyun		clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
568*4882a593Smuzhiyun		clock-names = "xvclk";
569*4882a593Smuzhiyun		power-domains = <&power RK3588_PD_VI>;
570*4882a593Smuzhiyun		pinctrl-names = "default";
571*4882a593Smuzhiyun		pinctrl-0 = <&mipim1_camera2_clk>;
572*4882a593Smuzhiyun		rockchip,grf = <&sys_grf>;
573*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
574*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
575*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
576*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
577*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-OT2016-FV1";
578*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
579*4882a593Smuzhiyun		port {
580*4882a593Smuzhiyun			ov13855_out: endpoint {
581*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
582*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
583*4882a593Smuzhiyun			};
584*4882a593Smuzhiyun		};
585*4882a593Smuzhiyun	};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun	ov50c40: ov50c40@36 {
588*4882a593Smuzhiyun		compatible = "ovti,ov50c40";
589*4882a593Smuzhiyun		status = "okay";
590*4882a593Smuzhiyun		reg = <0x36>;
591*4882a593Smuzhiyun		clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
592*4882a593Smuzhiyun		clock-names = "xvclk";
593*4882a593Smuzhiyun		power-domains = <&power RK3588_PD_VI>;
594*4882a593Smuzhiyun		pinctrl-names = "default";
595*4882a593Smuzhiyun		pinctrl-0 = <&mipim1_camera1_clk>;
596*4882a593Smuzhiyun		rockchip,grf = <&sys_grf>;
597*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
598*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
599*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
600*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
601*4882a593Smuzhiyun		rockchip,camera-module-name = "HZGA06";
602*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "ZE0082C1";
603*4882a593Smuzhiyun		eeprom-ctrl = <&otp_eeprom>;
604*4882a593Smuzhiyun		lens-focus = <&aw8601>;
605*4882a593Smuzhiyun		port {
606*4882a593Smuzhiyun			ov50c40_out: endpoint {
607*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ov50c40>;
608*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
609*4882a593Smuzhiyun			};
610*4882a593Smuzhiyun		};
611*4882a593Smuzhiyun	};
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun	otp_eeprom: otp_eeprom@50 {
614*4882a593Smuzhiyun		compatible = "rk,otp_eeprom";
615*4882a593Smuzhiyun		status = "okay";
616*4882a593Smuzhiyun		reg = <0x50>;
617*4882a593Smuzhiyun	};
618*4882a593Smuzhiyun};
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun&csi2_dcphy0 {
621*4882a593Smuzhiyun	status = "okay";
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun	ports {
624*4882a593Smuzhiyun		#address-cells = <1>;
625*4882a593Smuzhiyun		#size-cells = <0>;
626*4882a593Smuzhiyun		port@0 {
627*4882a593Smuzhiyun			reg = <0>;
628*4882a593Smuzhiyun			#address-cells = <1>;
629*4882a593Smuzhiyun			#size-cells = <0>;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun			mipi_in_ov50c40: endpoint@1 {
632*4882a593Smuzhiyun				reg = <1>;
633*4882a593Smuzhiyun				remote-endpoint = <&ov50c40_out>;
634*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
635*4882a593Smuzhiyun			};
636*4882a593Smuzhiyun		};
637*4882a593Smuzhiyun		port@1 {
638*4882a593Smuzhiyun			reg = <1>;
639*4882a593Smuzhiyun			#address-cells = <1>;
640*4882a593Smuzhiyun			#size-cells = <0>;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun			csidcphy0_out: endpoint@0 {
643*4882a593Smuzhiyun				reg = <0>;
644*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
645*4882a593Smuzhiyun			};
646*4882a593Smuzhiyun		};
647*4882a593Smuzhiyun	};
648*4882a593Smuzhiyun};
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun&csi2_dcphy1 {
651*4882a593Smuzhiyun	status = "okay";
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun	ports {
654*4882a593Smuzhiyun		#address-cells = <1>;
655*4882a593Smuzhiyun		#size-cells = <0>;
656*4882a593Smuzhiyun		port@0 {
657*4882a593Smuzhiyun			reg = <0>;
658*4882a593Smuzhiyun			#address-cells = <1>;
659*4882a593Smuzhiyun			#size-cells = <0>;
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
662*4882a593Smuzhiyun				reg = <1>;
663*4882a593Smuzhiyun				remote-endpoint = <&ov13855_out>;
664*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
665*4882a593Smuzhiyun			};
666*4882a593Smuzhiyun		};
667*4882a593Smuzhiyun		port@1 {
668*4882a593Smuzhiyun			reg = <1>;
669*4882a593Smuzhiyun			#address-cells = <1>;
670*4882a593Smuzhiyun			#size-cells = <0>;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun			csidcphy1_out: endpoint@0 {
673*4882a593Smuzhiyun				reg = <0>;
674*4882a593Smuzhiyun				remote-endpoint = <&mipi1_csi2_input>;
675*4882a593Smuzhiyun			};
676*4882a593Smuzhiyun		};
677*4882a593Smuzhiyun	};
678*4882a593Smuzhiyun};
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun&mipi_dcphy0 {
681*4882a593Smuzhiyun	status = "okay";
682*4882a593Smuzhiyun};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun&mipi_dcphy1 {
685*4882a593Smuzhiyun	status = "okay";
686*4882a593Smuzhiyun};
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun&mipi0_csi2 {
689*4882a593Smuzhiyun	status = "okay";
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun	ports {
692*4882a593Smuzhiyun		#address-cells = <1>;
693*4882a593Smuzhiyun		#size-cells = <0>;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun		port@0 {
696*4882a593Smuzhiyun			reg = <0>;
697*4882a593Smuzhiyun			#address-cells = <1>;
698*4882a593Smuzhiyun			#size-cells = <0>;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
701*4882a593Smuzhiyun				reg = <1>;
702*4882a593Smuzhiyun				remote-endpoint = <&csidcphy0_out>;
703*4882a593Smuzhiyun			};
704*4882a593Smuzhiyun		};
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun		port@1 {
707*4882a593Smuzhiyun			reg = <1>;
708*4882a593Smuzhiyun			#address-cells = <1>;
709*4882a593Smuzhiyun			#size-cells = <0>;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
712*4882a593Smuzhiyun				reg = <0>;
713*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
714*4882a593Smuzhiyun			};
715*4882a593Smuzhiyun		};
716*4882a593Smuzhiyun	};
717*4882a593Smuzhiyun};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun&mipi1_csi2 {
720*4882a593Smuzhiyun	status = "okay";
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun	ports {
723*4882a593Smuzhiyun		#address-cells = <1>;
724*4882a593Smuzhiyun		#size-cells = <0>;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun		port@0 {
727*4882a593Smuzhiyun			reg = <0>;
728*4882a593Smuzhiyun			#address-cells = <1>;
729*4882a593Smuzhiyun			#size-cells = <0>;
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun			mipi1_csi2_input: endpoint@1 {
732*4882a593Smuzhiyun				reg = <1>;
733*4882a593Smuzhiyun				remote-endpoint = <&csidcphy1_out>;
734*4882a593Smuzhiyun			};
735*4882a593Smuzhiyun		};
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun		port@1 {
738*4882a593Smuzhiyun			reg = <1>;
739*4882a593Smuzhiyun			#address-cells = <1>;
740*4882a593Smuzhiyun			#size-cells = <0>;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun			mipi1_csi2_output: endpoint@0 {
743*4882a593Smuzhiyun				reg = <0>;
744*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in1>;
745*4882a593Smuzhiyun			};
746*4882a593Smuzhiyun		};
747*4882a593Smuzhiyun	};
748*4882a593Smuzhiyun};
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun&i2c8 {
751*4882a593Smuzhiyun	status = "okay";
752*4882a593Smuzhiyun	pinctrl-names = "default";
753*4882a593Smuzhiyun	pinctrl-0 = <&i2c8m2_xfer>;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun	usbc0: fusb302@22 {
756*4882a593Smuzhiyun		compatible = "fcs,fusb302";
757*4882a593Smuzhiyun		reg = <0x22>;
758*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
759*4882a593Smuzhiyun		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
760*4882a593Smuzhiyun		int-n-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
761*4882a593Smuzhiyun		pinctrl-names = "default";
762*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
763*4882a593Smuzhiyun		vbus-supply = <&vbus5v0_typec>;
764*4882a593Smuzhiyun		status = "okay";
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun		ports {
767*4882a593Smuzhiyun			#address-cells = <1>;
768*4882a593Smuzhiyun			#size-cells = <0>;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun			port@0 {
771*4882a593Smuzhiyun				reg = <0>;
772*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
773*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
774*4882a593Smuzhiyun				};
775*4882a593Smuzhiyun			};
776*4882a593Smuzhiyun		};
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun		usb_con: connector {
779*4882a593Smuzhiyun			compatible = "usb-c-connector";
780*4882a593Smuzhiyun			label = "USB-C";
781*4882a593Smuzhiyun			data-role = "dual";
782*4882a593Smuzhiyun			power-role = "dual";
783*4882a593Smuzhiyun			try-power-role = "sink";
784*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
785*4882a593Smuzhiyun			sink-pdos =
786*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
787*4882a593Smuzhiyun				 PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
788*4882a593Smuzhiyun				 PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
789*4882a593Smuzhiyun			source-pdos =
790*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun			altmodes {
793*4882a593Smuzhiyun				#address-cells = <1>;
794*4882a593Smuzhiyun				#size-cells = <0>;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun				altmode@0 {
797*4882a593Smuzhiyun					reg = <0>;
798*4882a593Smuzhiyun					svid = <0xff01>;
799*4882a593Smuzhiyun					vdo = <0xffffffff>;
800*4882a593Smuzhiyun				};
801*4882a593Smuzhiyun			};
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun			ports {
804*4882a593Smuzhiyun				#address-cells = <1>;
805*4882a593Smuzhiyun				#size-cells = <0>;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun				port@0 {
808*4882a593Smuzhiyun					reg = <0>;
809*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
810*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_orientation_switch>;
811*4882a593Smuzhiyun					};
812*4882a593Smuzhiyun				};
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun				port@1 {
815*4882a593Smuzhiyun					reg = <1>;
816*4882a593Smuzhiyun					dp_altmode_mux: endpoint {
817*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
818*4882a593Smuzhiyun					};
819*4882a593Smuzhiyun				};
820*4882a593Smuzhiyun			};
821*4882a593Smuzhiyun		};
822*4882a593Smuzhiyun	};
823*4882a593Smuzhiyun};
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun&i2s0_8ch {
826*4882a593Smuzhiyun	status = "okay";
827*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
828*4882a593Smuzhiyun	pinctrl-0 = <&i2s0_lrck
829*4882a593Smuzhiyun		     &i2s0_sclk
830*4882a593Smuzhiyun		     &i2s0_sdi0
831*4882a593Smuzhiyun		     &i2s0_sdo0>;
832*4882a593Smuzhiyun};
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun&i2s2_2ch {
835*4882a593Smuzhiyun	pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>;
836*4882a593Smuzhiyun	rockchip,bclk-fs = <32>;
837*4882a593Smuzhiyun	status = "disabled";
838*4882a593Smuzhiyun};
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun&iep {
841*4882a593Smuzhiyun	status = "okay";
842*4882a593Smuzhiyun};
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun&iep_mmu {
845*4882a593Smuzhiyun	status = "okay";
846*4882a593Smuzhiyun};
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun&jpegd {
849*4882a593Smuzhiyun	status = "okay";
850*4882a593Smuzhiyun};
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun&jpegd_mmu {
853*4882a593Smuzhiyun	status = "okay";
854*4882a593Smuzhiyun};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun&jpege_ccu {
857*4882a593Smuzhiyun	status = "okay";
858*4882a593Smuzhiyun};
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun&jpege0 {
861*4882a593Smuzhiyun	status = "okay";
862*4882a593Smuzhiyun};
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun&jpege0_mmu {
865*4882a593Smuzhiyun	status = "okay";
866*4882a593Smuzhiyun};
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun&jpege1 {
869*4882a593Smuzhiyun	status = "okay";
870*4882a593Smuzhiyun};
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun&jpege1_mmu {
873*4882a593Smuzhiyun	status = "okay";
874*4882a593Smuzhiyun};
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun&jpege2 {
877*4882a593Smuzhiyun	status = "okay";
878*4882a593Smuzhiyun};
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun&jpege2_mmu {
881*4882a593Smuzhiyun	status = "okay";
882*4882a593Smuzhiyun};
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun&jpege3 {
885*4882a593Smuzhiyun	status = "okay";
886*4882a593Smuzhiyun};
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun&jpege3_mmu {
889*4882a593Smuzhiyun	status = "okay";
890*4882a593Smuzhiyun};
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun&mpp_srv {
893*4882a593Smuzhiyun	status = "okay";
894*4882a593Smuzhiyun};
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun&pcie2x1l2 {
897*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
898*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
899*4882a593Smuzhiyun	status = "okay";
900*4882a593Smuzhiyun};
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun&pdm0 {
903*4882a593Smuzhiyun	rockchip,path-map = <2 0 1 3>;
904*4882a593Smuzhiyun	status = "okay";
905*4882a593Smuzhiyun};
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun&pinctrl {
908*4882a593Smuzhiyun	cam {
909*4882a593Smuzhiyun		mipidcphy1_pwr: mipidcphy1-pwr {
910*4882a593Smuzhiyun			rockchip,pins =
911*4882a593Smuzhiyun				/* camera power en */
912*4882a593Smuzhiyun				<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
913*4882a593Smuzhiyun		};
914*4882a593Smuzhiyun	};
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun	charger {
917*4882a593Smuzhiyun		charger_ok: charger_ok {
918*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
919*4882a593Smuzhiyun		};
920*4882a593Smuzhiyun	};
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun	headphone {
923*4882a593Smuzhiyun		hp_det: hp-det {
924*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
925*4882a593Smuzhiyun		};
926*4882a593Smuzhiyun	};
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun	hym8563 {
929*4882a593Smuzhiyun		rtc_int: rtc-int {
930*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
931*4882a593Smuzhiyun		};
932*4882a593Smuzhiyun	};
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun	sensor {
935*4882a593Smuzhiyun		mpu6500_irq_gpio: mpu6500-irq-gpio {
936*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
937*4882a593Smuzhiyun		};
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun		mh248_irq_gpio: mh248-irq-gpio {
940*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
941*4882a593Smuzhiyun		};
942*4882a593Smuzhiyun	};
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun	touch {
945*4882a593Smuzhiyun		touch_gpio: touch-gpio {
946*4882a593Smuzhiyun			rockchip,pins =
947*4882a593Smuzhiyun				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
948*4882a593Smuzhiyun				<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
949*4882a593Smuzhiyun		};
950*4882a593Smuzhiyun	};
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun	usb {
953*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
954*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
955*4882a593Smuzhiyun		};
956*4882a593Smuzhiyun	};
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun	usb-typec {
959*4882a593Smuzhiyun		usbc0_int: usbc0-int {
960*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
961*4882a593Smuzhiyun		};
962*4882a593Smuzhiyun	};
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun	wireless-bluetooth {
965*4882a593Smuzhiyun		uart7_gpios: uart7-gpios {
966*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
967*4882a593Smuzhiyun		};
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
970*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
971*4882a593Smuzhiyun		};
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
974*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
975*4882a593Smuzhiyun		};
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
978*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
979*4882a593Smuzhiyun		};
980*4882a593Smuzhiyun	};
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun	wireless-wlan {
983*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
984*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
985*4882a593Smuzhiyun		};
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun		wifi_poweren_gpio: wifi-poweren-gpio {
988*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
989*4882a593Smuzhiyun		};
990*4882a593Smuzhiyun	};
991*4882a593Smuzhiyun};
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun&pwm12 {
994*4882a593Smuzhiyun	pinctrl-0 = <&pwm12m1_pins>;
995*4882a593Smuzhiyun	status = "okay";
996*4882a593Smuzhiyun};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun&rga3_core0 {
999*4882a593Smuzhiyun	status = "okay";
1000*4882a593Smuzhiyun};
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun&rga3_0_mmu {
1003*4882a593Smuzhiyun	status = "okay";
1004*4882a593Smuzhiyun};
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun&rga3_core1 {
1007*4882a593Smuzhiyun	status = "okay";
1008*4882a593Smuzhiyun};
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun&rga3_1_mmu {
1011*4882a593Smuzhiyun	status = "okay";
1012*4882a593Smuzhiyun};
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun&rga2 {
1015*4882a593Smuzhiyun	status = "okay";
1016*4882a593Smuzhiyun};
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun&rkcif {
1019*4882a593Smuzhiyun	status = "okay";
1020*4882a593Smuzhiyun};
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun&rkcif_mipi_lvds {
1023*4882a593Smuzhiyun	status = "okay";
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun	port {
1026*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
1027*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
1028*4882a593Smuzhiyun		};
1029*4882a593Smuzhiyun	};
1030*4882a593Smuzhiyun};
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
1033*4882a593Smuzhiyun	status = "okay";
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun	port {
1036*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
1037*4882a593Smuzhiyun			remote-endpoint = <&isp1_in1>;
1038*4882a593Smuzhiyun		};
1039*4882a593Smuzhiyun	};
1040*4882a593Smuzhiyun};
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun&rkcif_mipi_lvds1 {
1043*4882a593Smuzhiyun	status = "okay";
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun	port {
1046*4882a593Smuzhiyun		cif_mipi_in1: endpoint {
1047*4882a593Smuzhiyun			remote-endpoint = <&mipi1_csi2_output>;
1048*4882a593Smuzhiyun		};
1049*4882a593Smuzhiyun	};
1050*4882a593Smuzhiyun};
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun&rkcif_mipi_lvds1_sditf {
1053*4882a593Smuzhiyun	status = "okay";
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun	port {
1056*4882a593Smuzhiyun		mipi1_lvds_sditf: endpoint {
1057*4882a593Smuzhiyun			remote-endpoint = <&isp1_in2>;
1058*4882a593Smuzhiyun		};
1059*4882a593Smuzhiyun	};
1060*4882a593Smuzhiyun};
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun&rkcif_mmu {
1063*4882a593Smuzhiyun	status = "okay";
1064*4882a593Smuzhiyun};
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun&rkisp_unite {
1067*4882a593Smuzhiyun	status = "okay";
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun};
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun&rkisp_unite_mmu {
1072*4882a593Smuzhiyun	status = "okay";
1073*4882a593Smuzhiyun};
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun&rkisp0_vir0 {
1076*4882a593Smuzhiyun	status = "okay";
1077*4882a593Smuzhiyun	/*
1078*4882a593Smuzhiyun	 * dual isp process image case
1079*4882a593Smuzhiyun	 * other rkisp hw and virtual nodes should disabled
1080*4882a593Smuzhiyun	 */
1081*4882a593Smuzhiyun	rockchip,hw = <&rkisp_unite>;
1082*4882a593Smuzhiyun	port {
1083*4882a593Smuzhiyun		#address-cells = <1>;
1084*4882a593Smuzhiyun		#size-cells = <0>;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun		isp1_in1: endpoint@0 {
1087*4882a593Smuzhiyun			reg = <0>;
1088*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
1089*4882a593Smuzhiyun		};
1090*4882a593Smuzhiyun		isp1_in2: endpoint@1 {
1091*4882a593Smuzhiyun			reg = <1>;
1092*4882a593Smuzhiyun			remote-endpoint = <&mipi1_lvds_sditf>;
1093*4882a593Smuzhiyun		};
1094*4882a593Smuzhiyun	};
1095*4882a593Smuzhiyun};
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun&rknpu {
1098*4882a593Smuzhiyun	rknpu-supply = <&vdd_npu_s0>;
1099*4882a593Smuzhiyun	mem-supply = <&vdd_npu_mem_s0>;
1100*4882a593Smuzhiyun	status = "okay";
1101*4882a593Smuzhiyun};
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun&rknpu_mmu {
1104*4882a593Smuzhiyun	status = "okay";
1105*4882a593Smuzhiyun};
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun&rkvdec_ccu {
1108*4882a593Smuzhiyun	status = "okay";
1109*4882a593Smuzhiyun};
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun&rkvdec0 {
1112*4882a593Smuzhiyun	status = "okay";
1113*4882a593Smuzhiyun};
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun&rkvdec0_mmu {
1116*4882a593Smuzhiyun	status = "okay";
1117*4882a593Smuzhiyun};
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun&rkvdec1 {
1120*4882a593Smuzhiyun	status = "okay";
1121*4882a593Smuzhiyun};
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun&rkvdec1_mmu {
1124*4882a593Smuzhiyun	status = "okay";
1125*4882a593Smuzhiyun};
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun&rkvenc_ccu {
1128*4882a593Smuzhiyun	status = "okay";
1129*4882a593Smuzhiyun};
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun&rkvenc0 {
1132*4882a593Smuzhiyun	venc-supply = <&vdd_vdenc_s0>;
1133*4882a593Smuzhiyun	mem-supply = <&vdd_vdenc_mem_s0>;
1134*4882a593Smuzhiyun	status = "okay";
1135*4882a593Smuzhiyun};
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun&rkvenc0_mmu {
1138*4882a593Smuzhiyun	status = "okay";
1139*4882a593Smuzhiyun};
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun&rkvenc1 {
1142*4882a593Smuzhiyun	venc-supply = <&vdd_vdenc_s0>;
1143*4882a593Smuzhiyun	mem-supply = <&vdd_vdenc_mem_s0>;
1144*4882a593Smuzhiyun	status = "okay";
1145*4882a593Smuzhiyun};
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun&rkvenc1_mmu {
1148*4882a593Smuzhiyun	status = "okay";
1149*4882a593Smuzhiyun};
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun&rockchip_suspend {
1152*4882a593Smuzhiyun	status = "okay";
1153*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
1154*4882a593Smuzhiyun};
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun&route_edp0 {
1157*4882a593Smuzhiyun	connect = <&vp2_out_edp0>;
1158*4882a593Smuzhiyun	status = "okay";
1159*4882a593Smuzhiyun};
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun&saradc {
1162*4882a593Smuzhiyun	status = "okay";
1163*4882a593Smuzhiyun	vref-supply = <&avcc_1v8_s0>;
1164*4882a593Smuzhiyun};
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun&sdhci {
1167*4882a593Smuzhiyun	bus-width = <8>;
1168*4882a593Smuzhiyun	no-sdio;
1169*4882a593Smuzhiyun	no-sd;
1170*4882a593Smuzhiyun	non-removable;
1171*4882a593Smuzhiyun	max-frequency = <200000000>;
1172*4882a593Smuzhiyun	mmc-hs400-1_8v;
1173*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
1174*4882a593Smuzhiyun	status = "okay";
1175*4882a593Smuzhiyun};
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun&sdmmc {
1178*4882a593Smuzhiyun	max-frequency = <150000000>;
1179*4882a593Smuzhiyun	no-sdio;
1180*4882a593Smuzhiyun	no-mmc;
1181*4882a593Smuzhiyun	bus-width = <4>;
1182*4882a593Smuzhiyun	cap-mmc-highspeed;
1183*4882a593Smuzhiyun	cap-sd-highspeed;
1184*4882a593Smuzhiyun	disable-wp;
1185*4882a593Smuzhiyun	sd-uhs-sdr104;
1186*4882a593Smuzhiyun	vmmc-supply = <&vcc_3v3_sd_s0>;
1187*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd_s0>;
1188*4882a593Smuzhiyun	pinctrl-names = "default";
1189*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
1190*4882a593Smuzhiyun	status = "okay";
1191*4882a593Smuzhiyun};
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun&spdif_tx2 {
1194*4882a593Smuzhiyun	status = "okay";
1195*4882a593Smuzhiyun};
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun&tsadc {
1198*4882a593Smuzhiyun	status = "okay";
1199*4882a593Smuzhiyun};
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun&uart7 {
1202*4882a593Smuzhiyun	pinctrl-names = "default";
1203*4882a593Smuzhiyun	pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>;
1204*4882a593Smuzhiyun	status = "okay";
1205*4882a593Smuzhiyun};
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun&u2phy0 {
1208*4882a593Smuzhiyun	status = "okay";
1209*4882a593Smuzhiyun};
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun&u2phy2 {
1212*4882a593Smuzhiyun	status = "okay";
1213*4882a593Smuzhiyun};
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun&u2phy0_otg {
1216*4882a593Smuzhiyun	rockchip,typec-vbus-det;
1217*4882a593Smuzhiyun	status = "okay";
1218*4882a593Smuzhiyun};
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun&u2phy2_host {
1221*4882a593Smuzhiyun	status = "okay";
1222*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1223*4882a593Smuzhiyun};
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun&usb_host0_ehci {
1226*4882a593Smuzhiyun	status = "okay";
1227*4882a593Smuzhiyun};
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun&usb_host0_ohci {
1230*4882a593Smuzhiyun	status = "okay";
1231*4882a593Smuzhiyun};
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun&usbdp_phy0 {
1234*4882a593Smuzhiyun	orientation-switch;
1235*4882a593Smuzhiyun	svid = <0xff01>;
1236*4882a593Smuzhiyun	sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
1237*4882a593Smuzhiyun	sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>;
1238*4882a593Smuzhiyun	status = "okay";
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun	port {
1241*4882a593Smuzhiyun		#address-cells = <1>;
1242*4882a593Smuzhiyun		#size-cells = <0>;
1243*4882a593Smuzhiyun		usbdp_phy0_orientation_switch: endpoint@0 {
1244*4882a593Smuzhiyun			reg = <0>;
1245*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
1246*4882a593Smuzhiyun		};
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun		usbdp_phy0_dp_altmode_mux: endpoint@1 {
1249*4882a593Smuzhiyun			reg = <1>;
1250*4882a593Smuzhiyun			remote-endpoint = <&dp_altmode_mux>;
1251*4882a593Smuzhiyun		};
1252*4882a593Smuzhiyun	};
1253*4882a593Smuzhiyun};
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun&usbdp_phy0_dp {
1256*4882a593Smuzhiyun	status = "okay";
1257*4882a593Smuzhiyun};
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun&usbdp_phy0_u3 {
1260*4882a593Smuzhiyun	status = "okay";
1261*4882a593Smuzhiyun};
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun&usbdrd3_0 {
1264*4882a593Smuzhiyun	status = "okay";
1265*4882a593Smuzhiyun};
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1268*4882a593Smuzhiyun	dr_mode = "otg";
1269*4882a593Smuzhiyun	status = "okay";
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun	usb-role-switch;
1272*4882a593Smuzhiyun	port {
1273*4882a593Smuzhiyun		#address-cells = <1>;
1274*4882a593Smuzhiyun		#size-cells = <0>;
1275*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
1276*4882a593Smuzhiyun			reg = <0>;
1277*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1278*4882a593Smuzhiyun		};
1279*4882a593Smuzhiyun	};
1280*4882a593Smuzhiyun};
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun&usbhost3_0 {
1283*4882a593Smuzhiyun	status = "disabled";
1284*4882a593Smuzhiyun};
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun&usbhost_dwc3_0 {
1287*4882a593Smuzhiyun	status = "disabled";
1288*4882a593Smuzhiyun};
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun&vdpu {
1291*4882a593Smuzhiyun	status = "okay";
1292*4882a593Smuzhiyun};
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun&vdpu_mmu {
1295*4882a593Smuzhiyun	status = "okay";
1296*4882a593Smuzhiyun};
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun&vepu {
1299*4882a593Smuzhiyun	status = "okay";
1300*4882a593Smuzhiyun};
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun&vop {
1303*4882a593Smuzhiyun	status = "okay";
1304*4882a593Smuzhiyun};
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun&vop_mmu {
1307*4882a593Smuzhiyun	status = "okay";
1308*4882a593Smuzhiyun};
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun&vp1 {
1311*4882a593Smuzhiyun	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 |
1312*4882a593Smuzhiyun				1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
1313*4882a593Smuzhiyun	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
1314*4882a593Smuzhiyun};
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun&vp2 {
1317*4882a593Smuzhiyun	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 |
1318*4882a593Smuzhiyun				1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
1319*4882a593Smuzhiyun	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
1320*4882a593Smuzhiyun};
1321