xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
10*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
11*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
12*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h>
13*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
14*4882a593Smuzhiyun#include <dt-bindings/usb/pd.h>
15*4882a593Smuzhiyun#include "rk3588s.dtsi"
16*4882a593Smuzhiyun#include "rk3588-android.dtsi"
17*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/ {
20*4882a593Smuzhiyun	adc_keys: adc-keys {
21*4882a593Smuzhiyun		compatible = "adc-keys";
22*4882a593Smuzhiyun		io-channels = <&saradc 1>;
23*4882a593Smuzhiyun		io-channel-names = "buttons";
24*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
25*4882a593Smuzhiyun		poll-interval = <100>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		vol-up-key {
28*4882a593Smuzhiyun			label = "volume up";
29*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
30*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		vol-down-key {
34*4882a593Smuzhiyun			label = "volume down";
35*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
36*4882a593Smuzhiyun			press-threshold-microvolt = <890000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	backlight: backlight {
41*4882a593Smuzhiyun		compatible = "pwm-backlight";
42*4882a593Smuzhiyun		pwms = <&pwm13 0 25000 0>;
43*4882a593Smuzhiyun		brightness-levels = <
44*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
45*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
46*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
47*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
48*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
49*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
50*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
51*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
52*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
53*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
54*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
55*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
56*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
57*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
58*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
59*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
60*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
61*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
62*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
63*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
64*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
65*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
66*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
67*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
68*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
69*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
70*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
71*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
72*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
73*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
74*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
75*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
76*4882a593Smuzhiyun		>;
77*4882a593Smuzhiyun		default-brightness-level = <200>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	combophy_avdd0v85: combophy-avdd0v85 {
81*4882a593Smuzhiyun		compatible = "regulator-fixed";
82*4882a593Smuzhiyun		regulator-name = "combophy_avdd0v85";
83*4882a593Smuzhiyun		regulator-boot-on;
84*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
85*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
86*4882a593Smuzhiyun		vin-supply = <&vdd_0v85_s0>;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	combophy_avdd1v8: combophy-avdd1v8 {
90*4882a593Smuzhiyun		compatible = "regulator-fixed";
91*4882a593Smuzhiyun		regulator-name = "combophy_avdd1v8";
92*4882a593Smuzhiyun		regulator-boot-on;
93*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
94*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
95*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	charge-animation {
99*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
100*4882a593Smuzhiyun		rockchip,uboot-charge-on = <0>;
101*4882a593Smuzhiyun		rockchip,android-charge-on = <1>;
102*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3350>;
103*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3400>;
104*4882a593Smuzhiyun		status = "okay";
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	es8388_sound: es8388-sound {
108*4882a593Smuzhiyun		status = "okay";
109*4882a593Smuzhiyun		compatible = "simple-audio-card";
110*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
111*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
112*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,es8388-codec";
113*4882a593Smuzhiyun		simple-audio-card,aux-devs = <&aw87xxx_pa1 &aw87xxx_pa2>;
114*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
115*4882a593Smuzhiyun			format = "i2s";
116*4882a593Smuzhiyun			cpu {
117*4882a593Smuzhiyun				sound-dai = <&i2s0_8ch>;
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun			codec {
120*4882a593Smuzhiyun				sound-dai = <&es8388>;
121*4882a593Smuzhiyun			};
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	vcc3v3_lcd_n: vcc3v3-lcd0-n {
126*4882a593Smuzhiyun		compatible = "regulator-fixed";
127*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd0_n";
128*4882a593Smuzhiyun		regulator-boot-on;
129*4882a593Smuzhiyun		enable-active-high;
130*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
131*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s0>;
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	VDD5V8_LCD: vcc5v0-host {
135*4882a593Smuzhiyun		compatible = "regulator-fixed";
136*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
137*4882a593Smuzhiyun		regulator-boot-on;
138*4882a593Smuzhiyun		regulator-always-on;
139*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
140*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
141*4882a593Smuzhiyun		enable-active-high;
142*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
143*4882a593Smuzhiyun		/*vin-supply = <&vcc5v0_usb>;*/
144*4882a593Smuzhiyun		pinctrl-names = "default";
145*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	VEE5V8_LCD: vcc5v0-host1 {
149*4882a593Smuzhiyun		compatible = "regulator-fixed";
150*4882a593Smuzhiyun		regulator-name = "vcc5v0_host1";
151*4882a593Smuzhiyun		regulator-boot-on;
152*4882a593Smuzhiyun		regulator-always-on;
153*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
154*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
155*4882a593Smuzhiyun		enable-active-high;
156*4882a593Smuzhiyun		gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
157*4882a593Smuzhiyun		/*vin-supply = <&vcc5v0_usb>;*/
158*4882a593Smuzhiyun		pinctrl-names = "default";
159*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en1>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
163*4882a593Smuzhiyun		compatible = "regulator-fixed";
164*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
165*4882a593Smuzhiyun		regulator-always-on;
166*4882a593Smuzhiyun		regulator-boot-on;
167*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
168*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
172*4882a593Smuzhiyun		compatible = "regulator-fixed";
173*4882a593Smuzhiyun		regulator-name = "vcc_1v1_nldo_s3";
174*4882a593Smuzhiyun		regulator-always-on;
175*4882a593Smuzhiyun		regulator-boot-on;
176*4882a593Smuzhiyun		regulator-min-microvolt = <1100000>;
177*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
178*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
182*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
183*4882a593Smuzhiyun		clocks = <&hym8563>;
184*4882a593Smuzhiyun		clock-names = "ext_clock";
185*4882a593Smuzhiyun		uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
186*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
187*4882a593Smuzhiyun		pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>;
188*4882a593Smuzhiyun		pinctrl-1 = <&uart8_gpios>;
189*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
190*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
191*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
192*4882a593Smuzhiyun		status = "okay";
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
196*4882a593Smuzhiyun		compatible = "wlan-platdata";
197*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
198*4882a593Smuzhiyun		pinctrl-names = "default";
199*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
200*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
201*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
202*4882a593Smuzhiyun		status = "okay";
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&combphy0_ps {
207*4882a593Smuzhiyun	status = "okay";
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&combphy2_psu {
211*4882a593Smuzhiyun	status = "okay";
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&cpu_l0 {
215*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_lit_s0>;
216*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_lit_mem_s0>;
217*4882a593Smuzhiyun};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun&cpu_b0 {
220*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_big0_s0>;
221*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_big0_mem_s0>;
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&cpu_b2 {
225*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_big1_s0>;
226*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_big1_mem_s0>;
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&dmc {
230*4882a593Smuzhiyun	system-status-level = <
231*4882a593Smuzhiyun		/*system status         freq level*/
232*4882a593Smuzhiyun		SYS_STATUS_NORMAL       DMC_FREQ_LEVEL_MID_HIGH
233*4882a593Smuzhiyun		SYS_STATUS_REBOOT       DMC_FREQ_LEVEL_HIGH
234*4882a593Smuzhiyun		SYS_STATUS_SUSPEND      DMC_FREQ_LEVEL_LOW
235*4882a593Smuzhiyun		SYS_STATUS_BOOST        DMC_FREQ_LEVEL_HIGH
236*4882a593Smuzhiyun		SYS_STATUS_ISP          DMC_FREQ_LEVEL_HIGH
237*4882a593Smuzhiyun		SYS_STATUS_PERFORMANCE  DMC_FREQ_LEVEL_HIGH
238*4882a593Smuzhiyun		SYS_STATUS_DUALVIEW     DMC_FREQ_LEVEL_HIGH
239*4882a593Smuzhiyun	>;
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&dp0 {
243*4882a593Smuzhiyun	status = "disabled";
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&dp0_in_vp1 {
247*4882a593Smuzhiyun	status = "okay";
248*4882a593Smuzhiyun};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun&dsi0_in_vp2 {
251*4882a593Smuzhiyun	status = "okay";
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&dsi0_in_vp3 {
255*4882a593Smuzhiyun	status = "disabled";
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun/*
259*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled
260*4882a593Smuzhiyun * when dsi0 is enabled
261*4882a593Smuzhiyun */
262*4882a593Smuzhiyun&dsi0 {
263*4882a593Smuzhiyun	status = "okay";
264*4882a593Smuzhiyun	rockchip,dual-channel = <&dsi1>;
265*4882a593Smuzhiyun	//rockchip,lane-rate = <1000>;
266*4882a593Smuzhiyun	dsi0_panel: panel@0 {
267*4882a593Smuzhiyun		status = "okay";
268*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
269*4882a593Smuzhiyun		reg = <0>;
270*4882a593Smuzhiyun		backlight = <&backlight>;
271*4882a593Smuzhiyun		reset-delay-ms = <60>;
272*4882a593Smuzhiyun		enable-delay-ms = <60>;
273*4882a593Smuzhiyun		prepare-delay-ms = <60>;
274*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
275*4882a593Smuzhiyun		disable-delay-ms = <60>;
276*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
277*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
278*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
279*4882a593Smuzhiyun		dsi,lanes  = <4>;
280*4882a593Smuzhiyun		panel-init-sequence = [
281*4882a593Smuzhiyun			23 00 02 FE 21
282*4882a593Smuzhiyun			23 00 02 04 00
283*4882a593Smuzhiyun			23 00 02 00 64
284*4882a593Smuzhiyun			23 00 02 2A 00
285*4882a593Smuzhiyun			23 00 02 26 64
286*4882a593Smuzhiyun			23 00 02 54 00
287*4882a593Smuzhiyun			23 00 02 50 64
288*4882a593Smuzhiyun			23 00 02 7B 00
289*4882a593Smuzhiyun			23 00 02 77 64
290*4882a593Smuzhiyun			23 00 02 A2 00
291*4882a593Smuzhiyun			23 00 02 9D 64
292*4882a593Smuzhiyun			23 00 02 C9 00
293*4882a593Smuzhiyun			23 00 02 C5 64
294*4882a593Smuzhiyun			23 00 02 01 71
295*4882a593Smuzhiyun			23 00 02 27 71
296*4882a593Smuzhiyun			23 00 02 51 71
297*4882a593Smuzhiyun			23 00 02 78 71
298*4882a593Smuzhiyun			23 00 02 9E 71
299*4882a593Smuzhiyun			23 00 02 C6 71
300*4882a593Smuzhiyun			23 00 02 02 89
301*4882a593Smuzhiyun			23 00 02 28 89
302*4882a593Smuzhiyun			23 00 02 52 89
303*4882a593Smuzhiyun			23 00 02 79 89
304*4882a593Smuzhiyun			23 00 02 9F 89
305*4882a593Smuzhiyun			23 00 02 C7 89
306*4882a593Smuzhiyun			23 00 02 03 9E
307*4882a593Smuzhiyun			23 00 02 29 9E
308*4882a593Smuzhiyun			23 00 02 53 9E
309*4882a593Smuzhiyun			23 00 02 7A 9E
310*4882a593Smuzhiyun			23 00 02 A0 9E
311*4882a593Smuzhiyun			23 00 02 C8 9E
312*4882a593Smuzhiyun			23 00 02 09 00
313*4882a593Smuzhiyun			23 00 02 05 B0
314*4882a593Smuzhiyun			23 00 02 31 00
315*4882a593Smuzhiyun			23 00 02 2B B0
316*4882a593Smuzhiyun			23 00 02 5A 00
317*4882a593Smuzhiyun			23 00 02 55 B0
318*4882a593Smuzhiyun			23 00 02 80 00
319*4882a593Smuzhiyun			23 00 02 7C B0
320*4882a593Smuzhiyun			23 00 02 A7 00
321*4882a593Smuzhiyun			23 00 02 A3 B0
322*4882a593Smuzhiyun			23 00 02 CE 00
323*4882a593Smuzhiyun			23 00 02 CA B0
324*4882a593Smuzhiyun			23 00 02 06 C0
325*4882a593Smuzhiyun			23 00 02 2D C0
326*4882a593Smuzhiyun			23 00 02 56 C0
327*4882a593Smuzhiyun			23 00 02 7D C0
328*4882a593Smuzhiyun			23 00 02 A4 C0
329*4882a593Smuzhiyun			23 00 02 CB C0
330*4882a593Smuzhiyun			23 00 02 07 CF
331*4882a593Smuzhiyun			23 00 02 2F CF
332*4882a593Smuzhiyun			23 00 02 58 CF
333*4882a593Smuzhiyun			23 00 02 7E CF
334*4882a593Smuzhiyun			23 00 02 A5 CF
335*4882a593Smuzhiyun			23 00 02 CC CF
336*4882a593Smuzhiyun			23 00 02 08 DD
337*4882a593Smuzhiyun			23 00 02 30 DD
338*4882a593Smuzhiyun			23 00 02 59 DD
339*4882a593Smuzhiyun			23 00 02 7F DD
340*4882a593Smuzhiyun			23 00 02 A6 DD
341*4882a593Smuzhiyun			23 00 02 CD DD
342*4882a593Smuzhiyun			23 00 02 0E 15
343*4882a593Smuzhiyun			23 00 02 0A E9
344*4882a593Smuzhiyun			23 00 02 36 15
345*4882a593Smuzhiyun			23 00 02 32 E9
346*4882a593Smuzhiyun			23 00 02 5F 15
347*4882a593Smuzhiyun			23 00 02 5B E9
348*4882a593Smuzhiyun			23 00 02 85 15
349*4882a593Smuzhiyun			23 00 02 81 E9
350*4882a593Smuzhiyun			23 00 02 AD 15
351*4882a593Smuzhiyun			23 00 02 A9 E9
352*4882a593Smuzhiyun			23 00 02 D3 15
353*4882a593Smuzhiyun			23 00 02 CF E9
354*4882a593Smuzhiyun			23 00 02 0B 14
355*4882a593Smuzhiyun			23 00 02 33 14
356*4882a593Smuzhiyun			23 00 02 5C 14
357*4882a593Smuzhiyun			23 00 02 82 14
358*4882a593Smuzhiyun			23 00 02 AA 14
359*4882a593Smuzhiyun			23 00 02 D0 14
360*4882a593Smuzhiyun			23 00 02 0C 36
361*4882a593Smuzhiyun			23 00 02 34 36
362*4882a593Smuzhiyun			23 00 02 5D 36
363*4882a593Smuzhiyun			23 00 02 83 36
364*4882a593Smuzhiyun			23 00 02 AB 36
365*4882a593Smuzhiyun			23 00 02 D1 36
366*4882a593Smuzhiyun			23 00 02 0D 6B
367*4882a593Smuzhiyun			23 00 02 35 6B
368*4882a593Smuzhiyun			23 00 02 5E 6B
369*4882a593Smuzhiyun			23 00 02 84 6B
370*4882a593Smuzhiyun			23 00 02 AC 6B
371*4882a593Smuzhiyun			23 00 02 D2 6B
372*4882a593Smuzhiyun			23 00 02 13 5A
373*4882a593Smuzhiyun			23 00 02 0F 94
374*4882a593Smuzhiyun			23 00 02 3B 5A
375*4882a593Smuzhiyun			23 00 02 37 94
376*4882a593Smuzhiyun			23 00 02 64 5A
377*4882a593Smuzhiyun			23 00 02 60 94
378*4882a593Smuzhiyun			23 00 02 8A 5A
379*4882a593Smuzhiyun			23 00 02 86 94
380*4882a593Smuzhiyun			23 00 02 B2 5A
381*4882a593Smuzhiyun			23 00 02 AE 94
382*4882a593Smuzhiyun			23 00 02 D8 5A
383*4882a593Smuzhiyun			23 00 02 D4 94
384*4882a593Smuzhiyun			23 00 02 10 D1
385*4882a593Smuzhiyun			23 00 02 38 D1
386*4882a593Smuzhiyun			23 00 02 61 D1
387*4882a593Smuzhiyun			23 00 02 87 D1
388*4882a593Smuzhiyun			23 00 02 AF D1
389*4882a593Smuzhiyun			23 00 02 D5 D1
390*4882a593Smuzhiyun			23 00 02 11 04
391*4882a593Smuzhiyun			23 00 02 39 04
392*4882a593Smuzhiyun			23 00 02 62 04
393*4882a593Smuzhiyun			23 00 02 88 04
394*4882a593Smuzhiyun			23 00 02 B0 04
395*4882a593Smuzhiyun			23 00 02 D6 04
396*4882a593Smuzhiyun			23 00 02 12 05
397*4882a593Smuzhiyun			23 00 02 3A 05
398*4882a593Smuzhiyun			23 00 02 63 05
399*4882a593Smuzhiyun			23 00 02 89 05
400*4882a593Smuzhiyun			23 00 02 B1 05
401*4882a593Smuzhiyun			23 00 02 D7 05
402*4882a593Smuzhiyun			23 00 02 18 AA
403*4882a593Smuzhiyun			23 00 02 14 36
404*4882a593Smuzhiyun			23 00 02 42 AA
405*4882a593Smuzhiyun			23 00 02 3D 36
406*4882a593Smuzhiyun			23 00 02 69 AA
407*4882a593Smuzhiyun			23 00 02 65 36
408*4882a593Smuzhiyun			23 00 02 8F AA
409*4882a593Smuzhiyun			23 00 02 8B 36
410*4882a593Smuzhiyun			23 00 02 B7 AA
411*4882a593Smuzhiyun			23 00 02 B3 36
412*4882a593Smuzhiyun			23 00 02 DD AA
413*4882a593Smuzhiyun			23 00 02 D9 36
414*4882a593Smuzhiyun			23 00 02 15 74
415*4882a593Smuzhiyun			23 00 02 3F 74
416*4882a593Smuzhiyun			23 00 02 66 74
417*4882a593Smuzhiyun			23 00 02 8C 74
418*4882a593Smuzhiyun			23 00 02 B4 74
419*4882a593Smuzhiyun			23 00 02 DA 74
420*4882a593Smuzhiyun			23 00 02 16 9F
421*4882a593Smuzhiyun			23 00 02 40 9F
422*4882a593Smuzhiyun			23 00 02 67 9F
423*4882a593Smuzhiyun			23 00 02 8D 9F
424*4882a593Smuzhiyun			23 00 02 B5 9F
425*4882a593Smuzhiyun			23 00 02 DB 9F
426*4882a593Smuzhiyun			23 00 02 17 DC
427*4882a593Smuzhiyun			23 00 02 41 DC
428*4882a593Smuzhiyun			23 00 02 68 DC
429*4882a593Smuzhiyun			23 00 02 8E DC
430*4882a593Smuzhiyun			23 00 02 B6 DC
431*4882a593Smuzhiyun			23 00 02 DC DC
432*4882a593Smuzhiyun			23 00 02 1D FF
433*4882a593Smuzhiyun			23 00 02 19 03
434*4882a593Smuzhiyun			23 00 02 47 FF
435*4882a593Smuzhiyun			23 00 02 43 03
436*4882a593Smuzhiyun			23 00 02 6E FF
437*4882a593Smuzhiyun			23 00 02 6A 03
438*4882a593Smuzhiyun			23 00 02 94 FF
439*4882a593Smuzhiyun			23 00 02 90 03
440*4882a593Smuzhiyun			23 00 02 BC FF
441*4882a593Smuzhiyun			23 00 02 B8 03
442*4882a593Smuzhiyun			23 00 02 E2 FF
443*4882a593Smuzhiyun			23 00 02 DE 03
444*4882a593Smuzhiyun			23 00 02 1A 35
445*4882a593Smuzhiyun			23 00 02 44 35
446*4882a593Smuzhiyun			23 00 02 6B 35
447*4882a593Smuzhiyun			23 00 02 91 35
448*4882a593Smuzhiyun			23 00 02 B9 35
449*4882a593Smuzhiyun			23 00 02 DF 35
450*4882a593Smuzhiyun			23 00 02 1B 45
451*4882a593Smuzhiyun			23 00 02 45 45
452*4882a593Smuzhiyun			23 00 02 6C 45
453*4882a593Smuzhiyun			23 00 02 92 45
454*4882a593Smuzhiyun			23 00 02 BA 45
455*4882a593Smuzhiyun			23 00 02 E0 45
456*4882a593Smuzhiyun			23 00 02 1C 55
457*4882a593Smuzhiyun			23 00 02 46 55
458*4882a593Smuzhiyun			23 00 02 6D 55
459*4882a593Smuzhiyun			23 00 02 93 55
460*4882a593Smuzhiyun			23 00 02 BB 55
461*4882a593Smuzhiyun			23 00 02 E1 55
462*4882a593Smuzhiyun			23 00 02 22 FF
463*4882a593Smuzhiyun			23 00 02 1E 68
464*4882a593Smuzhiyun			23 00 02 4C FF
465*4882a593Smuzhiyun			23 00 02 48 68
466*4882a593Smuzhiyun			23 00 02 73 FF
467*4882a593Smuzhiyun			23 00 02 6F 68
468*4882a593Smuzhiyun			23 00 02 99 FF
469*4882a593Smuzhiyun			23 00 02 95 68
470*4882a593Smuzhiyun			23 00 02 C1 FF
471*4882a593Smuzhiyun			23 00 02 BD 68
472*4882a593Smuzhiyun			23 00 02 E7 FF
473*4882a593Smuzhiyun			23 00 02 E3 68
474*4882a593Smuzhiyun			23 00 02 1F 7E
475*4882a593Smuzhiyun			23 00 02 49 7E
476*4882a593Smuzhiyun			23 00 02 70 7E
477*4882a593Smuzhiyun			23 00 02 96 7E
478*4882a593Smuzhiyun			23 00 02 BE 7E
479*4882a593Smuzhiyun			23 00 02 E4 7E
480*4882a593Smuzhiyun			23 00 02 20 97
481*4882a593Smuzhiyun			23 00 02 4A 97
482*4882a593Smuzhiyun			23 00 02 71 97
483*4882a593Smuzhiyun			23 00 02 97 97
484*4882a593Smuzhiyun			23 00 02 BF 97
485*4882a593Smuzhiyun			23 00 02 E5 97
486*4882a593Smuzhiyun			23 00 02 21 B5
487*4882a593Smuzhiyun			23 00 02 4B B5
488*4882a593Smuzhiyun			23 00 02 72 B5
489*4882a593Smuzhiyun			23 00 02 98 B5
490*4882a593Smuzhiyun			23 00 02 C0 B5
491*4882a593Smuzhiyun			23 00 02 E6 B5
492*4882a593Smuzhiyun			23 00 02 25 F0
493*4882a593Smuzhiyun			23 00 02 23 E8
494*4882a593Smuzhiyun			23 00 02 4F F0
495*4882a593Smuzhiyun			23 00 02 4D E8
496*4882a593Smuzhiyun			23 00 02 76 F0
497*4882a593Smuzhiyun			23 00 02 74 E8
498*4882a593Smuzhiyun			23 00 02 9C F0
499*4882a593Smuzhiyun			23 00 02 9A E8
500*4882a593Smuzhiyun			23 00 02 C4 F0
501*4882a593Smuzhiyun			23 00 02 C2 E8
502*4882a593Smuzhiyun			23 00 02 EA F0
503*4882a593Smuzhiyun			23 00 02 E8 E8
504*4882a593Smuzhiyun			23 00 02 24 FF
505*4882a593Smuzhiyun			23 00 02 4E FF
506*4882a593Smuzhiyun			23 00 02 75 FF
507*4882a593Smuzhiyun			23 00 02 9B FF
508*4882a593Smuzhiyun			23 00 02 C3 FF
509*4882a593Smuzhiyun			23 00 02 E9 FF
510*4882a593Smuzhiyun			23 00 02 FE 3D
511*4882a593Smuzhiyun			23 00 02 00 04
512*4882a593Smuzhiyun			23 00 02 FE 23
513*4882a593Smuzhiyun			23 00 02 08 82
514*4882a593Smuzhiyun			23 00 02 0A 00
515*4882a593Smuzhiyun			23 00 02 0B 00
516*4882a593Smuzhiyun			23 00 02 0C 01
517*4882a593Smuzhiyun			23 00 02 16 00
518*4882a593Smuzhiyun			23 00 02 18 02
519*4882a593Smuzhiyun			23 00 02 1B 04
520*4882a593Smuzhiyun			23 00 02 19 04
521*4882a593Smuzhiyun			23 00 02 1C 81
522*4882a593Smuzhiyun			23 00 02 1F 00
523*4882a593Smuzhiyun			23 00 02 20 03
524*4882a593Smuzhiyun			23 00 02 23 04
525*4882a593Smuzhiyun			23 00 02 21 01
526*4882a593Smuzhiyun			23 00 02 54 63
527*4882a593Smuzhiyun			23 00 02 55 54
528*4882a593Smuzhiyun			23 00 02 6E 45
529*4882a593Smuzhiyun			23 00 02 6D 36
530*4882a593Smuzhiyun			23 00 02 FE 3D
531*4882a593Smuzhiyun			23 00 02 55 78
532*4882a593Smuzhiyun			23 00 02 FE 20
533*4882a593Smuzhiyun			23 00 02 26 30
534*4882a593Smuzhiyun			23 00 02 FE 3D
535*4882a593Smuzhiyun			23 00 02 20 71
536*4882a593Smuzhiyun			23 00 02 50 8F
537*4882a593Smuzhiyun			23 00 02 51 8F
538*4882a593Smuzhiyun			23 00 02 FE 00
539*4882a593Smuzhiyun			23 00 02 35 00
540*4882a593Smuzhiyun			05 78 01 11
541*4882a593Smuzhiyun			05 1E 01 29
542*4882a593Smuzhiyun		];
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun		panel-exit-sequence = [
545*4882a593Smuzhiyun			05 00 01 28
546*4882a593Smuzhiyun			05 00 01 10
547*4882a593Smuzhiyun		];
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun		disp_timings0: display-timings {
550*4882a593Smuzhiyun			native-mode = <&dsi0_timing0>;
551*4882a593Smuzhiyun			dsi0_timing0: timing0 {
552*4882a593Smuzhiyun				clock-frequency = <132000000>;
553*4882a593Smuzhiyun				hactive = <1080>;
554*4882a593Smuzhiyun				vactive = <1920>;
555*4882a593Smuzhiyun				hfront-porch = <15>;
556*4882a593Smuzhiyun				hsync-len = <4>;
557*4882a593Smuzhiyun				hback-porch = <30>;
558*4882a593Smuzhiyun				vfront-porch = <15>;
559*4882a593Smuzhiyun				vsync-len = <2>;
560*4882a593Smuzhiyun				vback-porch = <15>;
561*4882a593Smuzhiyun				hsync-active = <0>;
562*4882a593Smuzhiyun				vsync-active = <0>;
563*4882a593Smuzhiyun				de-active = <0>;
564*4882a593Smuzhiyun				pixelclk-active = <0>;
565*4882a593Smuzhiyun			};
566*4882a593Smuzhiyun		};
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun		ports {
569*4882a593Smuzhiyun			#address-cells = <1>;
570*4882a593Smuzhiyun			#size-cells = <0>;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun			port@0 {
573*4882a593Smuzhiyun				reg = <0>;
574*4882a593Smuzhiyun				panel_in_dsi: endpoint {
575*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
576*4882a593Smuzhiyun				};
577*4882a593Smuzhiyun			};
578*4882a593Smuzhiyun		};
579*4882a593Smuzhiyun	};
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun	ports {
582*4882a593Smuzhiyun		#address-cells = <1>;
583*4882a593Smuzhiyun		#size-cells = <0>;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun		port@1 {
586*4882a593Smuzhiyun			reg = <1>;
587*4882a593Smuzhiyun			dsi_out_panel: endpoint {
588*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
589*4882a593Smuzhiyun			};
590*4882a593Smuzhiyun		};
591*4882a593Smuzhiyun	};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun};
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun&dsi1 {
596*4882a593Smuzhiyun	status = "okay";
597*4882a593Smuzhiyun	//rockchip,lane-rate = <1000>;
598*4882a593Smuzhiyun	dsi1_panel: panel@0 {
599*4882a593Smuzhiyun		status = "okay";
600*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
601*4882a593Smuzhiyun		reg = <0>;
602*4882a593Smuzhiyun		backlight = <&backlight>;
603*4882a593Smuzhiyun		reset-delay-ms = <60>;
604*4882a593Smuzhiyun		enable-delay-ms = <60>;
605*4882a593Smuzhiyun		prepare-delay-ms = <60>;
606*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
607*4882a593Smuzhiyun		disable-delay-ms = <60>;
608*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
609*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
610*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
611*4882a593Smuzhiyun		dsi,lanes  = <4>;
612*4882a593Smuzhiyun		panel-init-sequence = [
613*4882a593Smuzhiyun			23 00 02 FE 21
614*4882a593Smuzhiyun			23 00 02 04 00
615*4882a593Smuzhiyun			23 00 02 00 64
616*4882a593Smuzhiyun			23 00 02 2A 00
617*4882a593Smuzhiyun			23 00 02 26 64
618*4882a593Smuzhiyun			23 00 02 54 00
619*4882a593Smuzhiyun			23 00 02 50 64
620*4882a593Smuzhiyun			23 00 02 7B 00
621*4882a593Smuzhiyun			23 00 02 77 64
622*4882a593Smuzhiyun			23 00 02 A2 00
623*4882a593Smuzhiyun			23 00 02 9D 64
624*4882a593Smuzhiyun			23 00 02 C9 00
625*4882a593Smuzhiyun			23 00 02 C5 64
626*4882a593Smuzhiyun			23 00 02 01 71
627*4882a593Smuzhiyun			23 00 02 27 71
628*4882a593Smuzhiyun			23 00 02 51 71
629*4882a593Smuzhiyun			23 00 02 78 71
630*4882a593Smuzhiyun			23 00 02 9E 71
631*4882a593Smuzhiyun			23 00 02 C6 71
632*4882a593Smuzhiyun			23 00 02 02 89
633*4882a593Smuzhiyun			23 00 02 28 89
634*4882a593Smuzhiyun			23 00 02 52 89
635*4882a593Smuzhiyun			23 00 02 79 89
636*4882a593Smuzhiyun			23 00 02 9F 89
637*4882a593Smuzhiyun			23 00 02 C7 89
638*4882a593Smuzhiyun			23 00 02 03 9E
639*4882a593Smuzhiyun			23 00 02 29 9E
640*4882a593Smuzhiyun			23 00 02 53 9E
641*4882a593Smuzhiyun			23 00 02 7A 9E
642*4882a593Smuzhiyun			23 00 02 A0 9E
643*4882a593Smuzhiyun			23 00 02 C8 9E
644*4882a593Smuzhiyun			23 00 02 09 00
645*4882a593Smuzhiyun			23 00 02 05 B0
646*4882a593Smuzhiyun			23 00 02 31 00
647*4882a593Smuzhiyun			23 00 02 2B B0
648*4882a593Smuzhiyun			23 00 02 5A 00
649*4882a593Smuzhiyun			23 00 02 55 B0
650*4882a593Smuzhiyun			23 00 02 80 00
651*4882a593Smuzhiyun			23 00 02 7C B0
652*4882a593Smuzhiyun			23 00 02 A7 00
653*4882a593Smuzhiyun			23 00 02 A3 B0
654*4882a593Smuzhiyun			23 00 02 CE 00
655*4882a593Smuzhiyun			23 00 02 CA B0
656*4882a593Smuzhiyun			23 00 02 06 C0
657*4882a593Smuzhiyun			23 00 02 2D C0
658*4882a593Smuzhiyun			23 00 02 56 C0
659*4882a593Smuzhiyun			23 00 02 7D C0
660*4882a593Smuzhiyun			23 00 02 A4 C0
661*4882a593Smuzhiyun			23 00 02 CB C0
662*4882a593Smuzhiyun			23 00 02 07 CF
663*4882a593Smuzhiyun			23 00 02 2F CF
664*4882a593Smuzhiyun			23 00 02 58 CF
665*4882a593Smuzhiyun			23 00 02 7E CF
666*4882a593Smuzhiyun			23 00 02 A5 CF
667*4882a593Smuzhiyun			23 00 02 CC CF
668*4882a593Smuzhiyun			23 00 02 08 DD
669*4882a593Smuzhiyun			23 00 02 30 DD
670*4882a593Smuzhiyun			23 00 02 59 DD
671*4882a593Smuzhiyun			23 00 02 7F DD
672*4882a593Smuzhiyun			23 00 02 A6 DD
673*4882a593Smuzhiyun			23 00 02 CD DD
674*4882a593Smuzhiyun			23 00 02 0E 15
675*4882a593Smuzhiyun			23 00 02 0A E9
676*4882a593Smuzhiyun			23 00 02 36 15
677*4882a593Smuzhiyun			23 00 02 32 E9
678*4882a593Smuzhiyun			23 00 02 5F 15
679*4882a593Smuzhiyun			23 00 02 5B E9
680*4882a593Smuzhiyun			23 00 02 85 15
681*4882a593Smuzhiyun			23 00 02 81 E9
682*4882a593Smuzhiyun			23 00 02 AD 15
683*4882a593Smuzhiyun			23 00 02 A9 E9
684*4882a593Smuzhiyun			23 00 02 D3 15
685*4882a593Smuzhiyun			23 00 02 CF E9
686*4882a593Smuzhiyun			23 00 02 0B 14
687*4882a593Smuzhiyun			23 00 02 33 14
688*4882a593Smuzhiyun			23 00 02 5C 14
689*4882a593Smuzhiyun			23 00 02 82 14
690*4882a593Smuzhiyun			23 00 02 AA 14
691*4882a593Smuzhiyun			23 00 02 D0 14
692*4882a593Smuzhiyun			23 00 02 0C 36
693*4882a593Smuzhiyun			23 00 02 34 36
694*4882a593Smuzhiyun			23 00 02 5D 36
695*4882a593Smuzhiyun			23 00 02 83 36
696*4882a593Smuzhiyun			23 00 02 AB 36
697*4882a593Smuzhiyun			23 00 02 D1 36
698*4882a593Smuzhiyun			23 00 02 0D 6B
699*4882a593Smuzhiyun			23 00 02 35 6B
700*4882a593Smuzhiyun			23 00 02 5E 6B
701*4882a593Smuzhiyun			23 00 02 84 6B
702*4882a593Smuzhiyun			23 00 02 AC 6B
703*4882a593Smuzhiyun			23 00 02 D2 6B
704*4882a593Smuzhiyun			23 00 02 13 5A
705*4882a593Smuzhiyun			23 00 02 0F 94
706*4882a593Smuzhiyun			23 00 02 3B 5A
707*4882a593Smuzhiyun			23 00 02 37 94
708*4882a593Smuzhiyun			23 00 02 64 5A
709*4882a593Smuzhiyun			23 00 02 60 94
710*4882a593Smuzhiyun			23 00 02 8A 5A
711*4882a593Smuzhiyun			23 00 02 86 94
712*4882a593Smuzhiyun			23 00 02 B2 5A
713*4882a593Smuzhiyun			23 00 02 AE 94
714*4882a593Smuzhiyun			23 00 02 D8 5A
715*4882a593Smuzhiyun			23 00 02 D4 94
716*4882a593Smuzhiyun			23 00 02 10 D1
717*4882a593Smuzhiyun			23 00 02 38 D1
718*4882a593Smuzhiyun			23 00 02 61 D1
719*4882a593Smuzhiyun			23 00 02 87 D1
720*4882a593Smuzhiyun			23 00 02 AF D1
721*4882a593Smuzhiyun			23 00 02 D5 D1
722*4882a593Smuzhiyun			23 00 02 11 04
723*4882a593Smuzhiyun			23 00 02 39 04
724*4882a593Smuzhiyun			23 00 02 62 04
725*4882a593Smuzhiyun			23 00 02 88 04
726*4882a593Smuzhiyun			23 00 02 B0 04
727*4882a593Smuzhiyun			23 00 02 D6 04
728*4882a593Smuzhiyun			23 00 02 12 05
729*4882a593Smuzhiyun			23 00 02 3A 05
730*4882a593Smuzhiyun			23 00 02 63 05
731*4882a593Smuzhiyun			23 00 02 89 05
732*4882a593Smuzhiyun			23 00 02 B1 05
733*4882a593Smuzhiyun			23 00 02 D7 05
734*4882a593Smuzhiyun			23 00 02 18 AA
735*4882a593Smuzhiyun			23 00 02 14 36
736*4882a593Smuzhiyun			23 00 02 42 AA
737*4882a593Smuzhiyun			23 00 02 3D 36
738*4882a593Smuzhiyun			23 00 02 69 AA
739*4882a593Smuzhiyun			23 00 02 65 36
740*4882a593Smuzhiyun			23 00 02 8F AA
741*4882a593Smuzhiyun			23 00 02 8B 36
742*4882a593Smuzhiyun			23 00 02 B7 AA
743*4882a593Smuzhiyun			23 00 02 B3 36
744*4882a593Smuzhiyun			23 00 02 DD AA
745*4882a593Smuzhiyun			23 00 02 D9 36
746*4882a593Smuzhiyun			23 00 02 15 74
747*4882a593Smuzhiyun			23 00 02 3F 74
748*4882a593Smuzhiyun			23 00 02 66 74
749*4882a593Smuzhiyun			23 00 02 8C 74
750*4882a593Smuzhiyun			23 00 02 B4 74
751*4882a593Smuzhiyun			23 00 02 DA 74
752*4882a593Smuzhiyun			23 00 02 16 9F
753*4882a593Smuzhiyun			23 00 02 40 9F
754*4882a593Smuzhiyun			23 00 02 67 9F
755*4882a593Smuzhiyun			23 00 02 8D 9F
756*4882a593Smuzhiyun			23 00 02 B5 9F
757*4882a593Smuzhiyun			23 00 02 DB 9F
758*4882a593Smuzhiyun			23 00 02 17 DC
759*4882a593Smuzhiyun			23 00 02 41 DC
760*4882a593Smuzhiyun			23 00 02 68 DC
761*4882a593Smuzhiyun			23 00 02 8E DC
762*4882a593Smuzhiyun			23 00 02 B6 DC
763*4882a593Smuzhiyun			23 00 02 DC DC
764*4882a593Smuzhiyun			23 00 02 1D FF
765*4882a593Smuzhiyun			23 00 02 19 03
766*4882a593Smuzhiyun			23 00 02 47 FF
767*4882a593Smuzhiyun			23 00 02 43 03
768*4882a593Smuzhiyun			23 00 02 6E FF
769*4882a593Smuzhiyun			23 00 02 6A 03
770*4882a593Smuzhiyun			23 00 02 94 FF
771*4882a593Smuzhiyun			23 00 02 90 03
772*4882a593Smuzhiyun			23 00 02 BC FF
773*4882a593Smuzhiyun			23 00 02 B8 03
774*4882a593Smuzhiyun			23 00 02 E2 FF
775*4882a593Smuzhiyun			23 00 02 DE 03
776*4882a593Smuzhiyun			23 00 02 1A 35
777*4882a593Smuzhiyun			23 00 02 44 35
778*4882a593Smuzhiyun			23 00 02 6B 35
779*4882a593Smuzhiyun			23 00 02 91 35
780*4882a593Smuzhiyun			23 00 02 B9 35
781*4882a593Smuzhiyun			23 00 02 DF 35
782*4882a593Smuzhiyun			23 00 02 1B 45
783*4882a593Smuzhiyun			23 00 02 45 45
784*4882a593Smuzhiyun			23 00 02 6C 45
785*4882a593Smuzhiyun			23 00 02 92 45
786*4882a593Smuzhiyun			23 00 02 BA 45
787*4882a593Smuzhiyun			23 00 02 E0 45
788*4882a593Smuzhiyun			23 00 02 1C 55
789*4882a593Smuzhiyun			23 00 02 46 55
790*4882a593Smuzhiyun			23 00 02 6D 55
791*4882a593Smuzhiyun			23 00 02 93 55
792*4882a593Smuzhiyun			23 00 02 BB 55
793*4882a593Smuzhiyun			23 00 02 E1 55
794*4882a593Smuzhiyun			23 00 02 22 FF
795*4882a593Smuzhiyun			23 00 02 1E 68
796*4882a593Smuzhiyun			23 00 02 4C FF
797*4882a593Smuzhiyun			23 00 02 48 68
798*4882a593Smuzhiyun			23 00 02 73 FF
799*4882a593Smuzhiyun			23 00 02 6F 68
800*4882a593Smuzhiyun			23 00 02 99 FF
801*4882a593Smuzhiyun			23 00 02 95 68
802*4882a593Smuzhiyun			23 00 02 C1 FF
803*4882a593Smuzhiyun			23 00 02 BD 68
804*4882a593Smuzhiyun			23 00 02 E7 FF
805*4882a593Smuzhiyun			23 00 02 E3 68
806*4882a593Smuzhiyun			23 00 02 1F 7E
807*4882a593Smuzhiyun			23 00 02 49 7E
808*4882a593Smuzhiyun			23 00 02 70 7E
809*4882a593Smuzhiyun			23 00 02 96 7E
810*4882a593Smuzhiyun			23 00 02 BE 7E
811*4882a593Smuzhiyun			23 00 02 E4 7E
812*4882a593Smuzhiyun			23 00 02 20 97
813*4882a593Smuzhiyun			23 00 02 4A 97
814*4882a593Smuzhiyun			23 00 02 71 97
815*4882a593Smuzhiyun			23 00 02 97 97
816*4882a593Smuzhiyun			23 00 02 BF 97
817*4882a593Smuzhiyun			23 00 02 E5 97
818*4882a593Smuzhiyun			23 00 02 21 B5
819*4882a593Smuzhiyun			23 00 02 4B B5
820*4882a593Smuzhiyun			23 00 02 72 B5
821*4882a593Smuzhiyun			23 00 02 98 B5
822*4882a593Smuzhiyun			23 00 02 C0 B5
823*4882a593Smuzhiyun			23 00 02 E6 B5
824*4882a593Smuzhiyun			23 00 02 25 F0
825*4882a593Smuzhiyun			23 00 02 23 E8
826*4882a593Smuzhiyun			23 00 02 4F F0
827*4882a593Smuzhiyun			23 00 02 4D E8
828*4882a593Smuzhiyun			23 00 02 76 F0
829*4882a593Smuzhiyun			23 00 02 74 E8
830*4882a593Smuzhiyun			23 00 02 9C F0
831*4882a593Smuzhiyun			23 00 02 9A E8
832*4882a593Smuzhiyun			23 00 02 C4 F0
833*4882a593Smuzhiyun			23 00 02 C2 E8
834*4882a593Smuzhiyun			23 00 02 EA F0
835*4882a593Smuzhiyun			23 00 02 E8 E8
836*4882a593Smuzhiyun			23 00 02 24 FF
837*4882a593Smuzhiyun			23 00 02 4E FF
838*4882a593Smuzhiyun			23 00 02 75 FF
839*4882a593Smuzhiyun			23 00 02 9B FF
840*4882a593Smuzhiyun			23 00 02 C3 FF
841*4882a593Smuzhiyun			23 00 02 E9 FF
842*4882a593Smuzhiyun			23 00 02 FE 3D
843*4882a593Smuzhiyun			23 00 02 00 04
844*4882a593Smuzhiyun			23 00 02 FE 23
845*4882a593Smuzhiyun			23 00 02 08 82
846*4882a593Smuzhiyun			23 00 02 0A 00
847*4882a593Smuzhiyun			23 00 02 0B 00
848*4882a593Smuzhiyun			23 00 02 0C 01
849*4882a593Smuzhiyun			23 00 02 16 00
850*4882a593Smuzhiyun			23 00 02 18 02
851*4882a593Smuzhiyun			23 00 02 1B 04
852*4882a593Smuzhiyun			23 00 02 19 04
853*4882a593Smuzhiyun			23 00 02 1C 81
854*4882a593Smuzhiyun			23 00 02 1F 00
855*4882a593Smuzhiyun			23 00 02 20 03
856*4882a593Smuzhiyun			23 00 02 23 04
857*4882a593Smuzhiyun			23 00 02 21 01
858*4882a593Smuzhiyun			23 00 02 54 63
859*4882a593Smuzhiyun			23 00 02 55 54
860*4882a593Smuzhiyun			23 00 02 6E 45
861*4882a593Smuzhiyun			23 00 02 6D 36
862*4882a593Smuzhiyun			23 00 02 FE 3D
863*4882a593Smuzhiyun			23 00 02 55 78
864*4882a593Smuzhiyun			23 00 02 FE 20
865*4882a593Smuzhiyun			23 00 02 26 30
866*4882a593Smuzhiyun			23 00 02 FE 3D
867*4882a593Smuzhiyun			23 00 02 20 71
868*4882a593Smuzhiyun			23 00 02 50 8F
869*4882a593Smuzhiyun			23 00 02 51 8F
870*4882a593Smuzhiyun			23 00 02 FE 00
871*4882a593Smuzhiyun			23 00 02 35 00
872*4882a593Smuzhiyun			05 78 01 11
873*4882a593Smuzhiyun			05 1E 01 29
874*4882a593Smuzhiyun		];
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun		panel-exit-sequence = [
877*4882a593Smuzhiyun			05 00 01 28
878*4882a593Smuzhiyun			05 00 01 10
879*4882a593Smuzhiyun		];
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun		disp_timings1: display-timings {
882*4882a593Smuzhiyun			native-mode = <&dsi1_timing0>;
883*4882a593Smuzhiyun			dsi1_timing0: timing0 {
884*4882a593Smuzhiyun				clock-frequency = <132000000>;
885*4882a593Smuzhiyun				hactive = <1080>;
886*4882a593Smuzhiyun				vactive = <1920>;
887*4882a593Smuzhiyun				hfront-porch = <15>;
888*4882a593Smuzhiyun				hsync-len = <4>;
889*4882a593Smuzhiyun				hback-porch = <30>;
890*4882a593Smuzhiyun				vfront-porch = <15>;
891*4882a593Smuzhiyun				vsync-len = <2>;
892*4882a593Smuzhiyun				vback-porch = <15>;
893*4882a593Smuzhiyun				hsync-active = <0>;
894*4882a593Smuzhiyun				vsync-active = <0>;
895*4882a593Smuzhiyun				de-active = <0>;
896*4882a593Smuzhiyun				pixelclk-active = <0>;
897*4882a593Smuzhiyun			};
898*4882a593Smuzhiyun		};
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun		ports {
901*4882a593Smuzhiyun			#address-cells = <1>;
902*4882a593Smuzhiyun			#size-cells = <0>;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun			port@0 {
905*4882a593Smuzhiyun				reg = <0>;
906*4882a593Smuzhiyun				panel_in_dsi1: endpoint {
907*4882a593Smuzhiyun					remote-endpoint = <&dsi1_out_panel>;
908*4882a593Smuzhiyun				};
909*4882a593Smuzhiyun			};
910*4882a593Smuzhiyun		};
911*4882a593Smuzhiyun	};
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun	ports {
914*4882a593Smuzhiyun		#address-cells = <1>;
915*4882a593Smuzhiyun		#size-cells = <0>;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun		port@1 {
918*4882a593Smuzhiyun			reg = <1>;
919*4882a593Smuzhiyun			dsi1_out_panel: endpoint {
920*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi1>;
921*4882a593Smuzhiyun			};
922*4882a593Smuzhiyun		};
923*4882a593Smuzhiyun	};
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun};
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun&dsi0_panel {
928*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
929*4882a593Smuzhiyun	reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
930*4882a593Smuzhiyun	pinctrl-names = "default";
931*4882a593Smuzhiyun	pinctrl-0 = <&lcd_rst_gpio>;
932*4882a593Smuzhiyun	dsi,lanes  = <8>;
933*4882a593Smuzhiyun	panel-init-sequence = [
934*4882a593Smuzhiyun		29 02 02 00 00
935*4882a593Smuzhiyun		29 02 03 99 95 27
936*4882a593Smuzhiyun		05 78 01 11
937*4882a593Smuzhiyun		05 01 01 29
938*4882a593Smuzhiyun		29 00 02 00 00
939*4882a593Smuzhiyun		29 01 03 99 00 00
940*4882a593Smuzhiyun	];
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun	panel-exit-sequence = [
943*4882a593Smuzhiyun		29 00 02 00 00
944*4882a593Smuzhiyun		29 00 03 99 95 27
945*4882a593Smuzhiyun		05 01 01 28
946*4882a593Smuzhiyun		05 01 01 10
947*4882a593Smuzhiyun	];
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun	disp_timings0: display-timings {
950*4882a593Smuzhiyun		native-mode = <&dsi0_timing0>;
951*4882a593Smuzhiyun		dsi0_timing0: timing0 {
952*4882a593Smuzhiyun			clock-frequency = <246000000>;
953*4882a593Smuzhiyun			hactive = <1600>;
954*4882a593Smuzhiyun			vactive = <2176>;
955*4882a593Smuzhiyun			hfront-porch = <18>;
956*4882a593Smuzhiyun			hsync-len = <8>;
957*4882a593Smuzhiyun			hback-porch = <32>;
958*4882a593Smuzhiyun			vfront-porch = <255>;
959*4882a593Smuzhiyun			vsync-len = <6>;
960*4882a593Smuzhiyun			vback-porch = <34>;
961*4882a593Smuzhiyun			hsync-active = <0>;
962*4882a593Smuzhiyun			vsync-active = <0>;
963*4882a593Smuzhiyun			de-active = <0>;
964*4882a593Smuzhiyun			pixelclk-active = <0>;
965*4882a593Smuzhiyun		};
966*4882a593Smuzhiyun	};
967*4882a593Smuzhiyun};
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun&dsi1_in_vp2 {
970*4882a593Smuzhiyun	status = "disabled";
971*4882a593Smuzhiyun};
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun&dsi1_in_vp3 {
974*4882a593Smuzhiyun	status = "disabled";
975*4882a593Smuzhiyun};
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun&dsi1_panel {
978*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
979*4882a593Smuzhiyun	compressed-data;
980*4882a593Smuzhiyun	/*
981*4882a593Smuzhiyun	 * because in hardware, the two screens share the reset pin,
982*4882a593Smuzhiyun	 * so reset-gpios need only in dsi1 enable and dsi0 disabled
983*4882a593Smuzhiyun	 * case.
984*4882a593Smuzhiyun	 */
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun	//reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
987*4882a593Smuzhiyun	//pinctrl-names = "default";
988*4882a593Smuzhiyun	//pinctrl-0 = <&lcd_rst_gpio>;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun	dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun	slice-width = <720>;
993*4882a593Smuzhiyun	slice-height = <65>;
994*4882a593Smuzhiyun	version-major = <1>;
995*4882a593Smuzhiyun	version-minor = <1>;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun	panel-init-sequence = [
998*4882a593Smuzhiyun		29 10 03 f0 5a 5a
999*4882a593Smuzhiyun		/* Dsc Setting */
1000*4882a593Smuzhiyun		/* Compression Enable */
1001*4882a593Smuzhiyun		07 10 01 01
1002*4882a593Smuzhiyun		/* Scaler Disable */
1003*4882a593Smuzhiyun		15 10 02 c3 00
1004*4882a593Smuzhiyun		/* PPS Setting */
1005*4882a593Smuzhiyun		0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00
1006*4882a593Smuzhiyun		29 10 03 f0 a5 a5
1007*4882a593Smuzhiyun		/** Sleep Out */
1008*4882a593Smuzhiyun		05 00 01 11
1009*4882a593Smuzhiyun		/* 4. Common Setting */
1010*4882a593Smuzhiyun		/* 4.1 TE(Vync) ON/OFF */
1011*4882a593Smuzhiyun		15 00 02 35 00
1012*4882a593Smuzhiyun		/* 4.2 CASET/PASET Setting */
1013*4882a593Smuzhiyun		39 00 05 2a 00 00 05 9F
1014*4882a593Smuzhiyun		39 00 05 2b 00 00 0c 2f
1015*4882a593Smuzhiyun		/* 4.3 TSP SYNC Setting */
1016*4882a593Smuzhiyun		39 00 03 f0 5a 5a
1017*4882a593Smuzhiyun		39 00 0a B9 01 c0 3c 0b 00 00 00 11 03
1018*4882a593Smuzhiyun		39 00 03 f0 a5 a5
1019*4882a593Smuzhiyun		/* FD(Fast Discharge) Setting */
1020*4882a593Smuzhiyun		39 00 03 f0 5a 5a
1021*4882a593Smuzhiyun		15 00 02 b0 45
1022*4882a593Smuzhiyun		15 00 02 b5 48
1023*4882a593Smuzhiyun		39 00 03 f0 a5 a5
1024*4882a593Smuzhiyun		/* 4.6 FFC Setting (MIPI CLK 529MHz) */
1025*4882a593Smuzhiyun		39 00 03 f0 5a 5a
1026*4882a593Smuzhiyun		39 00 03 fc 5a 5a
1027*4882a593Smuzhiyun		15 00 02 b0 1E
1028*4882a593Smuzhiyun		39 00 06 c5 09 10 b4 24 fb
1029*4882a593Smuzhiyun		39 00 03 f0 a5 a5
1030*4882a593Smuzhiyun		39 00 03 fc a5 a5
1031*4882a593Smuzhiyun		/* OSC Spread Setting */
1032*4882a593Smuzhiyun		39 00 03 f0 5a 5a
1033*4882a593Smuzhiyun		39 00 03 fc 5a 5a
1034*4882a593Smuzhiyun		15 00 02 b0 37
1035*4882a593Smuzhiyun		/* FFC Setting; 0x04 : Disable */
1036*4882a593Smuzhiyun		39 00 06 c5 04 ff 00 01 64
1037*4882a593Smuzhiyun		39 00 03 f0 a5 a5
1038*4882a593Smuzhiyun		39 00 03 fc a5 a5
1039*4882a593Smuzhiyun		/* Dither IP Setting */
1040*4882a593Smuzhiyun		39 00 03 FC 5A 5A
1041*4882a593Smuzhiyun		15 00 02 b0 86
1042*4882a593Smuzhiyun		15 00 02 eb 01
1043*4882a593Smuzhiyun		39 00 03 FC a5 a5
1044*4882a593Smuzhiyun		/* 5 Brightness Control */
1045*4882a593Smuzhiyun		/* 5.1 Dimming Setting */
1046*4882a593Smuzhiyun		39 10 03 f0 5a 5a
1047*4882a593Smuzhiyun		15 10 02 b0 05
1048*4882a593Smuzhiyun		15 10 02 b1 01
1049*4882a593Smuzhiyun		15 10 02 b0 02
1050*4882a593Smuzhiyun		15 10 02 b5 d3
1051*4882a593Smuzhiyun		15 10 02 53 20
1052*4882a593Smuzhiyun		39 10 03 f0 a5 a5
1053*4882a593Smuzhiyun		39 10 03 51 02 ff
1054*4882a593Smuzhiyun		05 32 01 29
1055*4882a593Smuzhiyun	];
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun	panel-exit-sequence = [
1058*4882a593Smuzhiyun		/* Display off */
1059*4882a593Smuzhiyun		05 14 01 28
1060*4882a593Smuzhiyun		/* Sleep In */
1061*4882a593Smuzhiyun		05 00 01 10
1062*4882a593Smuzhiyun		/* VCI stabilization setting */
1063*4882a593Smuzhiyun		39 00 03 f0 5a 5a
1064*4882a593Smuzhiyun		15 00 02 b0 05
1065*4882a593Smuzhiyun		15 00 02 f4 01
1066*4882a593Smuzhiyun		39 a0 03 f0 a5 a5
1067*4882a593Smuzhiyun	];
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun	disp_timings1: display-timings {
1070*4882a593Smuzhiyun		native-mode = <&dsi1_timing0>;
1071*4882a593Smuzhiyun		dsi1_timing0: timing0 {
1072*4882a593Smuzhiyun			clock-frequency = <280000000>;
1073*4882a593Smuzhiyun			hactive = <1140>;
1074*4882a593Smuzhiyun			vactive = <3120>;
1075*4882a593Smuzhiyun			hfront-porch = <16>;
1076*4882a593Smuzhiyun			hsync-len = <8>;
1077*4882a593Smuzhiyun			hback-porch = <8>;
1078*4882a593Smuzhiyun			vfront-porch = <4>;
1079*4882a593Smuzhiyun			vsync-len = <2>;
1080*4882a593Smuzhiyun			vback-porch = <16>;
1081*4882a593Smuzhiyun			hsync-active = <0>;
1082*4882a593Smuzhiyun			vsync-active = <0>;
1083*4882a593Smuzhiyun			de-active = <0>;
1084*4882a593Smuzhiyun			pixelclk-active = <0>;
1085*4882a593Smuzhiyun		};
1086*4882a593Smuzhiyun	};
1087*4882a593Smuzhiyun};
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun&gpu {
1090*4882a593Smuzhiyun	mali-supply = <&vdd_gpu_s0>;
1091*4882a593Smuzhiyun	mem-supply = <&vdd_gpu_mem_s0>;
1092*4882a593Smuzhiyun	upthreshold = <60>;
1093*4882a593Smuzhiyun	downdifferential = <30>;
1094*4882a593Smuzhiyun	status = "okay";
1095*4882a593Smuzhiyun};
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun&i2c0 {
1098*4882a593Smuzhiyun	status = "okay";
1099*4882a593Smuzhiyun	pinctrl-names = "default";
1100*4882a593Smuzhiyun	pinctrl-0 = <&i2c0m2_xfer>;
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
1103*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
1104*4882a593Smuzhiyun		reg = <0x42>;
1105*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
1106*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
1107*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big0_s0";
1108*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
1109*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
1110*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
1111*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
1112*4882a593Smuzhiyun		regulator-boot-on;
1113*4882a593Smuzhiyun		regulator-always-on;
1114*4882a593Smuzhiyun		regulator-state-mem {
1115*4882a593Smuzhiyun			regulator-off-in-suspend;
1116*4882a593Smuzhiyun		};
1117*4882a593Smuzhiyun	};
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
1120*4882a593Smuzhiyun		compatible = "rockchip,rk8603";
1121*4882a593Smuzhiyun		reg = <0x43>;
1122*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
1123*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
1124*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big1_s0";
1125*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
1126*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
1127*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
1128*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
1129*4882a593Smuzhiyun		regulator-boot-on;
1130*4882a593Smuzhiyun		regulator-always-on;
1131*4882a593Smuzhiyun		regulator-state-mem {
1132*4882a593Smuzhiyun			regulator-off-in-suspend;
1133*4882a593Smuzhiyun		};
1134*4882a593Smuzhiyun	};
1135*4882a593Smuzhiyun};
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun&i2c2 {
1138*4882a593Smuzhiyun	status = "okay";
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun	cw2015@62 {
1141*4882a593Smuzhiyun		status = "okay";
1142*4882a593Smuzhiyun		compatible = "cellwise,cw2015";
1143*4882a593Smuzhiyun		reg = <0x62>;
1144*4882a593Smuzhiyun		cellwise,battery-profile = /bits/ 8
1145*4882a593Smuzhiyun			<0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B
1146*4882a593Smuzhiyun			 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D
1147*4882a593Smuzhiyun			 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49
1148*4882a593Smuzhiyun			 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49
1149*4882a593Smuzhiyun			 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35
1150*4882a593Smuzhiyun			 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17
1151*4882a593Smuzhiyun			 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB
1152*4882a593Smuzhiyun			 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>;
1153*4882a593Smuzhiyun		cellwise,monitor-interval-ms = <5000>;
1154*4882a593Smuzhiyun		power-supplies = <&bq25895>;
1155*4882a593Smuzhiyun	};
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun	bq25895: charger@6a {
1158*4882a593Smuzhiyun		compatible = "ti,bq25895", "ti,bq25890";
1159*4882a593Smuzhiyun		reg = <0x6a>;
1160*4882a593Smuzhiyun		pinctrl-names = "default";
1161*4882a593Smuzhiyun		pinctrl-0 = <&charger_ok>;
1162*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
1163*4882a593Smuzhiyun		interrupts = <RK_PC3 IRQ_TYPE_EDGE_FALLING>;
1164*4882a593Smuzhiyun		otg-mode-en-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
1165*4882a593Smuzhiyun		ti,usb-charger-detection = <&usbc0>;
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun		ti,battery-regulation-voltage = <4400000>; /* 4.4V */
1168*4882a593Smuzhiyun		ti,charge-current = <1600000>; /* 1.6A */
1169*4882a593Smuzhiyun		ti,termination-current = <66000>;  /* 66mA */
1170*4882a593Smuzhiyun		ti,precharge-current = <130000>; /* 130mA */
1171*4882a593Smuzhiyun		ti,minimum-sys-voltage = <3000000>; /* 3V */
1172*4882a593Smuzhiyun		ti,boost-voltage = <5000000>; /* 5V */
1173*4882a593Smuzhiyun		ti,boost-max-current = <1600000>; /* 1600mA */
1174*4882a593Smuzhiyun		regulators {
1175*4882a593Smuzhiyun			vbus5v0_typec: vbus5v0-typec {
1176*4882a593Smuzhiyun				regulator-compatible = "otg-vbus";
1177*4882a593Smuzhiyun				regulator-name = "vbus5v0_typec";
1178*4882a593Smuzhiyun			};
1179*4882a593Smuzhiyun		};
1180*4882a593Smuzhiyun	};
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun	vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
1183*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
1184*4882a593Smuzhiyun		reg = <0x42>;
1185*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
1186*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
1187*4882a593Smuzhiyun		regulator-name = "vdd_npu_s0";
1188*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
1189*4882a593Smuzhiyun		regulator-max-microvolt = <950000>;
1190*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
1191*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
1192*4882a593Smuzhiyun		regulator-boot-on;
1193*4882a593Smuzhiyun		regulator-always-on;
1194*4882a593Smuzhiyun		regulator-state-mem {
1195*4882a593Smuzhiyun			regulator-off-in-suspend;
1196*4882a593Smuzhiyun		};
1197*4882a593Smuzhiyun	};
1198*4882a593Smuzhiyun};
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun&i2c3 {
1201*4882a593Smuzhiyun	status = "okay";
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun	es8388: es8388@11 {
1204*4882a593Smuzhiyun		status = "okay";
1205*4882a593Smuzhiyun		#sound-dai-cells = <0>;
1206*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
1207*4882a593Smuzhiyun		reg = <0x11>;
1208*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
1209*4882a593Smuzhiyun		clock-names = "mclk";
1210*4882a593Smuzhiyun		pinctrl-names = "default";
1211*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
1212*4882a593Smuzhiyun	};
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun	aw87xxx_pa1: aw87xxx_pa1@58 {
1215*4882a593Smuzhiyun		compatible = "awinic,aw87xxx_pa";
1216*4882a593Smuzhiyun		#sound-dai-cells = <0>;
1217*4882a593Smuzhiyun		reg = <0x58>;
1218*4882a593Smuzhiyun		dev_index = < 0 >;
1219*4882a593Smuzhiyun		status = "okay";
1220*4882a593Smuzhiyun	};
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun	aw87xxx_pa2: aw87xxx_pa2@59 {
1223*4882a593Smuzhiyun		compatible = "awinic,aw87xxx_pa";
1224*4882a593Smuzhiyun		#sound-dai-cells = <0>;
1225*4882a593Smuzhiyun		reg = <0x59>;
1226*4882a593Smuzhiyun		dev_index = < 1 >;
1227*4882a593Smuzhiyun		status = "okay";
1228*4882a593Smuzhiyun	};
1229*4882a593Smuzhiyun};
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun&i2c4 {
1232*4882a593Smuzhiyun	status = "okay";
1233*4882a593Smuzhiyun	pinctrl-names = "default";
1234*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m3_xfer>;
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun	focaltech: focaltech@38 {
1237*4882a593Smuzhiyun		status = "okay";
1238*4882a593Smuzhiyun		compatible = "focaltech,fts";
1239*4882a593Smuzhiyun		reg = <0x38>;
1240*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
1241*4882a593Smuzhiyun		pinctrl-names = "default";
1242*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
1243*4882a593Smuzhiyun		focaltech,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
1244*4882a593Smuzhiyun		focaltech,reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
1245*4882a593Smuzhiyun		focaltech,have-key = <0>;
1246*4882a593Smuzhiyun		focaltech,key-number = <3>;
1247*4882a593Smuzhiyun		focaltech,keys = <256 1068 64 64 128 1068 64 64 192 1068 64 64>;
1248*4882a593Smuzhiyun		focaltech,key-x-coord = <1600>;
1249*4882a593Smuzhiyun		focaltech,key-y-coord = <2176>;
1250*4882a593Smuzhiyun		focaltech,max-touch-number = <5>;
1251*4882a593Smuzhiyun	};
1252*4882a593Smuzhiyun};
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun&i2c5 {
1255*4882a593Smuzhiyun	status = "okay";
1256*4882a593Smuzhiyun	pinctrl-names = "default";
1257*4882a593Smuzhiyun	//pinctrl-0 = <&i2c5m3_xfer>;
1258*4882a593Smuzhiyun	pinctrl-0 = <&i2c5m0_xfer>;
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun	ls_ucs14620: light@38 {
1261*4882a593Smuzhiyun		compatible = "ls_ucs14620";
1262*4882a593Smuzhiyun		status = "okay";
1263*4882a593Smuzhiyun		reg = <0x38>;
1264*4882a593Smuzhiyun		type = <SENSOR_TYPE_LIGHT>;
1265*4882a593Smuzhiyun		irq_enable = <0>;
1266*4882a593Smuzhiyun		als_threshold_high = <100>;
1267*4882a593Smuzhiyun		als_threshold_low = <10>;
1268*4882a593Smuzhiyun		als_ctrl_gain = <3>;/* 0:x1 1:x4 2:x16 3:x64 */
1269*4882a593Smuzhiyun		als_ctrl_time = <0x9f>;
1270*4882a593Smuzhiyun		poll_delay_ms = <100>;
1271*4882a593Smuzhiyun	};
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun	ps_ucs14620: proximity@38 {
1274*4882a593Smuzhiyun		status = "okay";
1275*4882a593Smuzhiyun		compatible = "ps_ucs14620";
1276*4882a593Smuzhiyun		reg = <0x38>;
1277*4882a593Smuzhiyun		type = <SENSOR_TYPE_PROXIMITY>;
1278*4882a593Smuzhiyun		//pinctrl-names = "default";
1279*4882a593Smuzhiyun		//pinctrl-0 = <&gpio3_c6>;
1280*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
1281*4882a593Smuzhiyun		irq_enable = <0>;
1282*4882a593Smuzhiyun		ps_threshold_high = <0x20>;
1283*4882a593Smuzhiyun		ps_threshold_low = <0x1d>;
1284*4882a593Smuzhiyun		ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */
1285*4882a593Smuzhiyun		ps_led_current = <3>; /* 0:12.5mA 1:100mA 2:150mA 3:200mA*/
1286*4882a593Smuzhiyun		poll_delay_ms = <100>;
1287*4882a593Smuzhiyun	};
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun	regulator@3e {
1290*4882a593Smuzhiyun		compatible = "tps65132";
1291*4882a593Smuzhiyun		reg = <0x3e>;
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun		outp {
1294*4882a593Smuzhiyun			regulator-name = "LCD_AVDD"; //P
1295*4882a593Smuzhiyun			vin-supply = <&vcc5v0_sys>;
1296*4882a593Smuzhiyun			/*pinctrl-names = "default";*/
1297*4882a593Smuzhiyun			/*pinctrl-0 = <&pinctrl_dsibiasen>;*/
1298*4882a593Smuzhiyun			/*enable = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;*/
1299*4882a593Smuzhiyun			/*enable-active-high;*/
1300*4882a593Smuzhiyun		};
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun		outn {
1303*4882a593Smuzhiyun			regulator-name = "LCD_AVEE";
1304*4882a593Smuzhiyun			vin-supply = <&vcc5v0_sys>;
1305*4882a593Smuzhiyun			/*enable = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;*/
1306*4882a593Smuzhiyun		};
1307*4882a593Smuzhiyun	};
1308*4882a593Smuzhiyun};
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun&i2c8 {
1311*4882a593Smuzhiyun	status = "okay";
1312*4882a593Smuzhiyun	pinctrl-names = "default";
1313*4882a593Smuzhiyun	pinctrl-0 = <&i2c8m2_xfer>;
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun	usbc0: fusb302@22 {
1316*4882a593Smuzhiyun		compatible = "fcs,fusb302";
1317*4882a593Smuzhiyun		reg = <0x22>;
1318*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
1319*4882a593Smuzhiyun		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
1320*4882a593Smuzhiyun		int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
1321*4882a593Smuzhiyun		pinctrl-names = "default";
1322*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
1323*4882a593Smuzhiyun		vbus-supply = <&vbus5v0_typec>;
1324*4882a593Smuzhiyun		status = "okay";
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun		ports {
1327*4882a593Smuzhiyun			#address-cells = <1>;
1328*4882a593Smuzhiyun			#size-cells = <0>;
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun			port@0 {
1331*4882a593Smuzhiyun				reg = <0>;
1332*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
1333*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
1334*4882a593Smuzhiyun				};
1335*4882a593Smuzhiyun			};
1336*4882a593Smuzhiyun		};
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun		usb_con: connector {
1339*4882a593Smuzhiyun			compatible = "usb-c-connector";
1340*4882a593Smuzhiyun			label = "USB-C";
1341*4882a593Smuzhiyun			data-role = "dual";
1342*4882a593Smuzhiyun			power-role = "dual";
1343*4882a593Smuzhiyun			try-power-role = "sink";
1344*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
1345*4882a593Smuzhiyun			sink-pdos =
1346*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
1347*4882a593Smuzhiyun				 PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
1348*4882a593Smuzhiyun				 PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
1349*4882a593Smuzhiyun			source-pdos =
1350*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun			ports {
1353*4882a593Smuzhiyun				#address-cells = <1>;
1354*4882a593Smuzhiyun				#size-cells = <0>;
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun				port@0 {
1357*4882a593Smuzhiyun					reg = <0>;
1358*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
1359*4882a593Smuzhiyun						remote-endpoint = <&u2phy0_orientation_switch>;
1360*4882a593Smuzhiyun					};
1361*4882a593Smuzhiyun				};
1362*4882a593Smuzhiyun			};
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun		};
1365*4882a593Smuzhiyun	};
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun	hym8563: hym8563@51 {
1368*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
1369*4882a593Smuzhiyun		reg = <0x51>;
1370*4882a593Smuzhiyun		#clock-cells = <0>;
1371*4882a593Smuzhiyun		clock-frequency = <32768>;
1372*4882a593Smuzhiyun		clock-output-names = "hym8563";
1373*4882a593Smuzhiyun		pinctrl-names = "default";
1374*4882a593Smuzhiyun		pinctrl-0 = <&hym8563_int>;
1375*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
1376*4882a593Smuzhiyun		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
1377*4882a593Smuzhiyun		wakeup-source;
1378*4882a593Smuzhiyun		status = "okay";
1379*4882a593Smuzhiyun	};
1380*4882a593Smuzhiyun};
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun&i2s0_8ch {
1383*4882a593Smuzhiyun	status = "okay";
1384*4882a593Smuzhiyun	pinctrl-0 = <&i2s0_lrck
1385*4882a593Smuzhiyun		     &i2s0_sclk
1386*4882a593Smuzhiyun		     &i2s0_sdi0
1387*4882a593Smuzhiyun		     &i2s0_sdo0>;
1388*4882a593Smuzhiyun};
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun&iep {
1391*4882a593Smuzhiyun	status = "okay";
1392*4882a593Smuzhiyun};
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun&iep_mmu {
1395*4882a593Smuzhiyun	status = "okay";
1396*4882a593Smuzhiyun};
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun&jpegd {
1399*4882a593Smuzhiyun	status = "okay";
1400*4882a593Smuzhiyun};
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun&jpegd_mmu {
1403*4882a593Smuzhiyun	status = "okay";
1404*4882a593Smuzhiyun};
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun&jpege0 {
1407*4882a593Smuzhiyun	status = "okay";
1408*4882a593Smuzhiyun};
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun&jpege0_mmu {
1411*4882a593Smuzhiyun	status = "okay";
1412*4882a593Smuzhiyun};
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun&mipi_dcphy0 {
1415*4882a593Smuzhiyun	status = "okay";
1416*4882a593Smuzhiyun};
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun&mipi_dcphy1 {
1419*4882a593Smuzhiyun	status = "okay";
1420*4882a593Smuzhiyun};
1421*4882a593Smuzhiyun
1422*4882a593Smuzhiyun&mpp_srv {
1423*4882a593Smuzhiyun	status = "okay";
1424*4882a593Smuzhiyun};
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun&pcie2x1l2 {
1427*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
1428*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
1429*4882a593Smuzhiyun	status = "okay";
1430*4882a593Smuzhiyun};
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun&pdm0 {
1433*4882a593Smuzhiyun	status = "okay";
1434*4882a593Smuzhiyun};
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun&pinctrl {
1437*4882a593Smuzhiyun	charger {
1438*4882a593Smuzhiyun		charger_ok: charger_ok {
1439*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
1440*4882a593Smuzhiyun					<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
1441*4882a593Smuzhiyun		};
1442*4882a593Smuzhiyun	};
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun	hym8563 {
1445*4882a593Smuzhiyun		hym8563_int: hym8563-int {
1446*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
1447*4882a593Smuzhiyun		};
1448*4882a593Smuzhiyun	};
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun	lcd {
1451*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
1452*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1453*4882a593Smuzhiyun		};
1454*4882a593Smuzhiyun	};
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun	touch {
1457*4882a593Smuzhiyun		touch_gpio: touch-gpio {
1458*4882a593Smuzhiyun			rockchip,pins =
1459*4882a593Smuzhiyun				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
1460*4882a593Smuzhiyun				<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
1461*4882a593Smuzhiyun		};
1462*4882a593Smuzhiyun	};
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun	usb {
1465*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
1466*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
1467*4882a593Smuzhiyun		};
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun		vcc5v0_host_en1: vcc5v0-host-en1 {
1470*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1471*4882a593Smuzhiyun		};
1472*4882a593Smuzhiyun	};
1473*4882a593Smuzhiyun
1474*4882a593Smuzhiyun	usb-typec {
1475*4882a593Smuzhiyun		usbc0_int: usbc0-int {
1476*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
1477*4882a593Smuzhiyun		};
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun		/*
1480*4882a593Smuzhiyun		 *typec5v_pwren: typec5v-pwren {
1481*4882a593Smuzhiyun		 *        rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
1482*4882a593Smuzhiyun		 *};
1483*4882a593Smuzhiyun		 */
1484*4882a593Smuzhiyun	};
1485*4882a593Smuzhiyun
1486*4882a593Smuzhiyun	wireless-bluetooth {
1487*4882a593Smuzhiyun		uart8_gpios: uart8-gpios {
1488*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1489*4882a593Smuzhiyun		};
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
1492*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
1493*4882a593Smuzhiyun		};
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
1496*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
1497*4882a593Smuzhiyun		};
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun		bt_wake_host_irq: bt-wake-host-irq {
1500*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
1501*4882a593Smuzhiyun		};
1502*4882a593Smuzhiyun	};
1503*4882a593Smuzhiyun
1504*4882a593Smuzhiyun	wireless-wlan {
1505*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
1506*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
1507*4882a593Smuzhiyun		};
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun		wifi_poweren_gpio: wifi-poweren-gpio {
1510*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
1511*4882a593Smuzhiyun		};
1512*4882a593Smuzhiyun	};
1513*4882a593Smuzhiyun};
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun&pwm13 {
1516*4882a593Smuzhiyun	status = "okay";
1517*4882a593Smuzhiyun	pinctrl-names = "active";
1518*4882a593Smuzhiyun	pinctrl-0 = <&pwm13m1_pins>;
1519*4882a593Smuzhiyun};
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun&rga2 {
1522*4882a593Smuzhiyun	status = "okay";
1523*4882a593Smuzhiyun};
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun&rga3_core0 {
1526*4882a593Smuzhiyun	status = "okay";
1527*4882a593Smuzhiyun};
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun&rga3_0_mmu {
1530*4882a593Smuzhiyun	status = "okay";
1531*4882a593Smuzhiyun};
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun&rga3_core1 {
1534*4882a593Smuzhiyun	status = "okay";
1535*4882a593Smuzhiyun};
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun&rga3_1_mmu {
1538*4882a593Smuzhiyun	status = "okay";
1539*4882a593Smuzhiyun};
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun&rkvdec_ccu {
1542*4882a593Smuzhiyun	status = "okay";
1543*4882a593Smuzhiyun};
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun&rkvdec0 {
1546*4882a593Smuzhiyun	status = "okay";
1547*4882a593Smuzhiyun};
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun&rkvdec0_mmu {
1550*4882a593Smuzhiyun	status = "okay";
1551*4882a593Smuzhiyun};
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun&rkvenc0 {
1554*4882a593Smuzhiyun	venc-supply = <&vdd_vdenc_s0>;
1555*4882a593Smuzhiyun	mem-supply = <&vdd_vdenc_mem_s0>;
1556*4882a593Smuzhiyun	status = "okay";
1557*4882a593Smuzhiyun};
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun&rkvenc0_mmu {
1560*4882a593Smuzhiyun	status = "okay";
1561*4882a593Smuzhiyun};
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun&rockchip_suspend {
1564*4882a593Smuzhiyun	status = "okay";
1565*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
1566*4882a593Smuzhiyun};
1567*4882a593Smuzhiyun
1568*4882a593Smuzhiyun&route_dsi0 {
1569*4882a593Smuzhiyun	status = "okay";
1570*4882a593Smuzhiyun	connect = <&vp2_out_dsi0>;
1571*4882a593Smuzhiyun};
1572*4882a593Smuzhiyun
1573*4882a593Smuzhiyun&saradc {
1574*4882a593Smuzhiyun	status = "okay";
1575*4882a593Smuzhiyun	vref-supply = <&vcc_1v8_s0>;
1576*4882a593Smuzhiyun};
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun&sdhci {
1579*4882a593Smuzhiyun	bus-width = <8>;
1580*4882a593Smuzhiyun	no-sdio;
1581*4882a593Smuzhiyun	no-sd;
1582*4882a593Smuzhiyun	non-removable;
1583*4882a593Smuzhiyun	max-frequency = <200000000>;
1584*4882a593Smuzhiyun	mmc-hs400-1_8v;
1585*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
1586*4882a593Smuzhiyun	status = "okay";
1587*4882a593Smuzhiyun};
1588*4882a593Smuzhiyun
1589*4882a593Smuzhiyun&spi2 {
1590*4882a593Smuzhiyun	status = "okay";
1591*4882a593Smuzhiyun	pinctrl-names = "default";
1592*4882a593Smuzhiyun	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
1593*4882a593Smuzhiyun	num-cs = <1>;
1594*4882a593Smuzhiyun};
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun&tsadc {
1597*4882a593Smuzhiyun	status = "okay";
1598*4882a593Smuzhiyun};
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun&uart8 {
1601*4882a593Smuzhiyun	status = "okay";
1602*4882a593Smuzhiyun	pinctrl-names = "default";
1603*4882a593Smuzhiyun	pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>;
1604*4882a593Smuzhiyun};
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun&u2phy0 {
1607*4882a593Smuzhiyun	orientation-switch;
1608*4882a593Smuzhiyun	status = "okay";
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun	port {
1611*4882a593Smuzhiyun		#address-cells = <1>;
1612*4882a593Smuzhiyun		#size-cells = <0>;
1613*4882a593Smuzhiyun		u2phy0_orientation_switch: endpoint@0 {
1614*4882a593Smuzhiyun			reg = <0>;
1615*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
1616*4882a593Smuzhiyun		};
1617*4882a593Smuzhiyun	};
1618*4882a593Smuzhiyun};
1619*4882a593Smuzhiyun
1620*4882a593Smuzhiyun&u2phy0_otg {
1621*4882a593Smuzhiyun	rockchip,sel-pipe-phystatus;
1622*4882a593Smuzhiyun	rockchip,typec-vbus-det;
1623*4882a593Smuzhiyun	status = "okay";
1624*4882a593Smuzhiyun};
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun&usbdrd3_0 {
1627*4882a593Smuzhiyun	status = "okay";
1628*4882a593Smuzhiyun};
1629*4882a593Smuzhiyun
1630*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1631*4882a593Smuzhiyun	dr_mode = "otg";
1632*4882a593Smuzhiyun	status = "okay";
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun	maximum-speed = "high-speed";
1635*4882a593Smuzhiyun	phys = <&u2phy0_otg>;
1636*4882a593Smuzhiyun	phy-names = "usb2-phy";
1637*4882a593Smuzhiyun	usb-role-switch;
1638*4882a593Smuzhiyun	port {
1639*4882a593Smuzhiyun		#address-cells = <1>;
1640*4882a593Smuzhiyun		#size-cells = <0>;
1641*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
1642*4882a593Smuzhiyun			reg = <0>;
1643*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1644*4882a593Smuzhiyun		};
1645*4882a593Smuzhiyun	};
1646*4882a593Smuzhiyun};
1647*4882a593Smuzhiyun
1648*4882a593Smuzhiyun&vdpu {
1649*4882a593Smuzhiyun	status = "okay";
1650*4882a593Smuzhiyun};
1651*4882a593Smuzhiyun
1652*4882a593Smuzhiyun&vdpu_mmu {
1653*4882a593Smuzhiyun	status = "okay";
1654*4882a593Smuzhiyun};
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun&vop {
1657*4882a593Smuzhiyun	status = "okay";
1658*4882a593Smuzhiyun};
1659*4882a593Smuzhiyun
1660*4882a593Smuzhiyun&vop_mmu {
1661*4882a593Smuzhiyun	status = "okay";
1662*4882a593Smuzhiyun};
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun&vp1 {
1665*4882a593Smuzhiyun	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 |
1666*4882a593Smuzhiyun				1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
1667*4882a593Smuzhiyun	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
1668*4882a593Smuzhiyun};
1669*4882a593Smuzhiyun
1670*4882a593Smuzhiyun&vp2 {
1671*4882a593Smuzhiyun	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 |
1672*4882a593Smuzhiyun				1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
1673*4882a593Smuzhiyun	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
1674*4882a593Smuzhiyun};
1675