xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-camera.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	vcc_mipidcphy0: vcc-mipidcphy0-regulator {
8*4882a593Smuzhiyun		compatible = "regulator-fixed";
9*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
10*4882a593Smuzhiyun		pinctrl-names = "default";
11*4882a593Smuzhiyun		pinctrl-0 = <&mipidcphy0_pwr>;
12*4882a593Smuzhiyun		regulator-name = "vcc_mipidcphy0";
13*4882a593Smuzhiyun		enable-active-high;
14*4882a593Smuzhiyun		regulator-boot-on;
15*4882a593Smuzhiyun		regulator-always-on;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun&csi2_dcphy0 {
20*4882a593Smuzhiyun	status = "okay";
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	ports {
23*4882a593Smuzhiyun		#address-cells = <1>;
24*4882a593Smuzhiyun		#size-cells = <0>;
25*4882a593Smuzhiyun		port@0 {
26*4882a593Smuzhiyun			reg = <0>;
27*4882a593Smuzhiyun			#address-cells = <1>;
28*4882a593Smuzhiyun			#size-cells = <0>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
31*4882a593Smuzhiyun				reg = <1>;
32*4882a593Smuzhiyun				remote-endpoint = <&s5k3l6_out0>;
33*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
34*4882a593Smuzhiyun			};
35*4882a593Smuzhiyun		};
36*4882a593Smuzhiyun		port@1 {
37*4882a593Smuzhiyun			reg = <1>;
38*4882a593Smuzhiyun			#address-cells = <1>;
39*4882a593Smuzhiyun			#size-cells = <0>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			csidcphy0_out: endpoint@0 {
42*4882a593Smuzhiyun				reg = <0>;
43*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
44*4882a593Smuzhiyun			};
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&i2c6 {
50*4882a593Smuzhiyun	status = "okay";
51*4882a593Smuzhiyun	pinctrl-names = "default";
52*4882a593Smuzhiyun	pinctrl-0 = <&i2c6m4_xfer>;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	fp5510: fp5510@c {
55*4882a593Smuzhiyun		compatible = "fitipower,fp5510";
56*4882a593Smuzhiyun		status = "okay";
57*4882a593Smuzhiyun		reg = <0x0c>;
58*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
59*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	s5k3l6: s5k3l6@10 {
63*4882a593Smuzhiyun		compatible = "samsung,s5k3l6xx";
64*4882a593Smuzhiyun		reg = <0x10>;
65*4882a593Smuzhiyun		clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
66*4882a593Smuzhiyun		clock-names = "xvclk";
67*4882a593Smuzhiyun		power-domains = <&power RK3588_PD_VI>;
68*4882a593Smuzhiyun		pinctrl-names = "default";
69*4882a593Smuzhiyun		pinctrl-0 = <&mipim1_camera1_clk>;
70*4882a593Smuzhiyun		// power-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
71*4882a593Smuzhiyun		reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
72*4882a593Smuzhiyun		//pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
73*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
74*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
75*4882a593Smuzhiyun		rockchip,camera-module-name = "default";
76*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
77*4882a593Smuzhiyun		lens-focus = <&fp5510>;
78*4882a593Smuzhiyun		port {
79*4882a593Smuzhiyun			s5k3l6_out0: endpoint {
80*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
81*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun&mipi_dcphy0 {
88*4882a593Smuzhiyun	status = "okay";
89*4882a593Smuzhiyun};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun&mipi0_csi2 {
92*4882a593Smuzhiyun	status = "okay";
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	ports {
95*4882a593Smuzhiyun		#address-cells = <1>;
96*4882a593Smuzhiyun		#size-cells = <0>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		port@0 {
99*4882a593Smuzhiyun			reg = <0>;
100*4882a593Smuzhiyun			#address-cells = <1>;
101*4882a593Smuzhiyun			#size-cells = <0>;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
104*4882a593Smuzhiyun				reg = <1>;
105*4882a593Smuzhiyun				remote-endpoint = <&csidcphy0_out>;
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		port@1 {
110*4882a593Smuzhiyun			reg = <1>;
111*4882a593Smuzhiyun			#address-cells = <1>;
112*4882a593Smuzhiyun			#size-cells = <0>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
115*4882a593Smuzhiyun				reg = <0>;
116*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
117*4882a593Smuzhiyun			};
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&rkcif {
123*4882a593Smuzhiyun	status = "okay";
124*4882a593Smuzhiyun};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun&rkcif_mipi_lvds {
127*4882a593Smuzhiyun	status = "okay";
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	port {
130*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
131*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
137*4882a593Smuzhiyun	status = "okay";
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	port {
140*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
141*4882a593Smuzhiyun			remote-endpoint = <&isp0_vir0>;
142*4882a593Smuzhiyun		};
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&rkcif_mmu {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&rkisp0 {
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&isp0_mmu {
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&rkisp0_vir0 {
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	port {
162*4882a593Smuzhiyun		#address-cells = <1>;
163*4882a593Smuzhiyun		#size-cells = <0>;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun		isp0_vir0: endpoint@0 {
166*4882a593Smuzhiyun			reg = <0>;
167*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&pinctrl {
173*4882a593Smuzhiyun	cam {
174*4882a593Smuzhiyun		mipidcphy0_pwr: mipidcphy0-pwr {
175*4882a593Smuzhiyun			rockchip,pins =
176*4882a593Smuzhiyun				/* camera power en */
177*4882a593Smuzhiyun				<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
178*4882a593Smuzhiyun		};
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun};
181