1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6/ { 7 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 8 compatible = "regulator-fixed"; 9 gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; 10 pinctrl-names = "default"; 11 pinctrl-0 = <&mipidcphy0_pwr>; 12 regulator-name = "vcc_mipidcphy0"; 13 enable-active-high; 14 regulator-boot-on; 15 regulator-always-on; 16 }; 17}; 18 19&csi2_dcphy0 { 20 status = "okay"; 21 22 ports { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 port@0 { 26 reg = <0>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 mipi_in_ucam0: endpoint@1 { 31 reg = <1>; 32 remote-endpoint = <&s5k3l6_out0>; 33 data-lanes = <1 2 3 4>; 34 }; 35 }; 36 port@1 { 37 reg = <1>; 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 csidcphy0_out: endpoint@0 { 42 reg = <0>; 43 remote-endpoint = <&mipi0_csi2_input>; 44 }; 45 }; 46 }; 47}; 48 49&i2c6 { 50 status = "okay"; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&i2c6m4_xfer>; 53 54 fp5510: fp5510@c { 55 compatible = "fitipower,fp5510"; 56 status = "okay"; 57 reg = <0x0c>; 58 rockchip,camera-module-index = <0>; 59 rockchip,camera-module-facing = "back"; 60 }; 61 62 s5k3l6: s5k3l6@10 { 63 compatible = "samsung,s5k3l6xx"; 64 reg = <0x10>; 65 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 66 clock-names = "xvclk"; 67 power-domains = <&power RK3588_PD_VI>; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&mipim1_camera1_clk>; 70 // power-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; 71 reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 72 //pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; 73 rockchip,camera-module-index = <0>; 74 rockchip,camera-module-facing = "back"; 75 rockchip,camera-module-name = "default"; 76 rockchip,camera-module-lens-name = "default"; 77 lens-focus = <&fp5510>; 78 port { 79 s5k3l6_out0: endpoint { 80 remote-endpoint = <&mipi_in_ucam0>; 81 data-lanes = <1 2 3 4>; 82 }; 83 }; 84 }; 85}; 86 87&mipi_dcphy0 { 88 status = "okay"; 89}; 90 91&mipi0_csi2 { 92 status = "okay"; 93 94 ports { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 port@0 { 99 reg = <0>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 mipi0_csi2_input: endpoint@1 { 104 reg = <1>; 105 remote-endpoint = <&csidcphy0_out>; 106 }; 107 }; 108 109 port@1 { 110 reg = <1>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 114 mipi0_csi2_output: endpoint@0 { 115 reg = <0>; 116 remote-endpoint = <&cif_mipi_in0>; 117 }; 118 }; 119 }; 120}; 121 122&rkcif { 123 status = "okay"; 124}; 125 126&rkcif_mipi_lvds { 127 status = "okay"; 128 129 port { 130 cif_mipi_in0: endpoint { 131 remote-endpoint = <&mipi0_csi2_output>; 132 }; 133 }; 134}; 135 136&rkcif_mipi_lvds_sditf { 137 status = "okay"; 138 139 port { 140 mipi_lvds_sditf: endpoint { 141 remote-endpoint = <&isp0_vir0>; 142 }; 143 }; 144}; 145 146&rkcif_mmu { 147 status = "okay"; 148}; 149 150&rkisp0 { 151 status = "okay"; 152}; 153 154&isp0_mmu { 155 status = "okay"; 156}; 157 158&rkisp0_vir0 { 159 status = "okay"; 160 161 port { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 isp0_vir0: endpoint@0 { 166 reg = <0>; 167 remote-endpoint = <&mipi_lvds_sditf>; 168 }; 169 }; 170}; 171 172&pinctrl { 173 cam { 174 mipidcphy0_pwr: mipidcphy0-pwr { 175 rockchip,pins = 176 /* camera power en */ 177 <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 178 }; 179 }; 180}; 181