xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun&spi2 {
11*4882a593Smuzhiyun	status = "okay";
12*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_SPI2>;
13*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
14*4882a593Smuzhiyun	num-cs = <2>;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	rk806master: rk806master@0 {
17*4882a593Smuzhiyun		compatible = "rockchip,rk806";
18*4882a593Smuzhiyun		spi-max-frequency = <1000000>;
19*4882a593Smuzhiyun		reg = <0x0>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
22*4882a593Smuzhiyun		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-power-off";
25*4882a593Smuzhiyun		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
26*4882a593Smuzhiyun		pinctrl-1 = <&rk806_dvs1_pwrdn>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		/* 2800mv-3500mv */
29*4882a593Smuzhiyun		low_voltage_threshold = <3000>;
30*4882a593Smuzhiyun		/* 2700mv-3400mv */
31*4882a593Smuzhiyun		shutdown_voltage_threshold = <2700>;
32*4882a593Smuzhiyun		/* 140 160 */
33*4882a593Smuzhiyun		shutdown_temperture_threshold = <160>;
34*4882a593Smuzhiyun		hotdie_temperture_threshold = <115>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		/* 0: restart PMU;
37*4882a593Smuzhiyun		 * 1: reset all the power off reset registers,
38*4882a593Smuzhiyun		 *    forcing the state to switch to ACTIVE mode;
39*4882a593Smuzhiyun		 * 2: Reset all the power off reset registers,
40*4882a593Smuzhiyun		 *    forcing the state to switch to ACTIVE mode,
41*4882a593Smuzhiyun		 *    and simultaneously pull down the RESETB PIN for 5mS before releasing
42*4882a593Smuzhiyun		 */
43*4882a593Smuzhiyun		pmic-reset-func = <1>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		/* PWRON_ON_TIME: 0:500mS; 1:20mS */
46*4882a593Smuzhiyun		pwron-on-time-20ms;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
49*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
50*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
51*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
52*4882a593Smuzhiyun		vcc5-supply = <&vcc5v0_sys>;
53*4882a593Smuzhiyun		vcc6-supply = <&vcc5v0_sys>;
54*4882a593Smuzhiyun		vcc7-supply = <&vcc5v0_sys>;
55*4882a593Smuzhiyun		vcc8-supply = <&vcc5v0_sys>;
56*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
57*4882a593Smuzhiyun		vcc10-supply = <&vcc5v0_sys>;
58*4882a593Smuzhiyun		vcc11-supply = <&vcc_2v0_pldo_s3>;
59*4882a593Smuzhiyun		vcc12-supply = <&vcc5v0_sys>;
60*4882a593Smuzhiyun		vcc13-supply = <&vcc5v0_sys>;
61*4882a593Smuzhiyun		vcc14-supply = <&vcc_1v1_nldo_s3>;
62*4882a593Smuzhiyun		vcca-supply = <&vcc5v0_sys>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		pwrkey {
65*4882a593Smuzhiyun			status = "okay";
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun		pinctrl_rk806: pinctrl_rk806 {
69*4882a593Smuzhiyun			gpio-controller;
70*4882a593Smuzhiyun			#gpio-cells = <2>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun			rk806_dvs1_null: rk806_dvs1_null {
73*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
74*4882a593Smuzhiyun				function = "pin_fun0";
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun			rk806_dvs1_slp: rk806_dvs1_slp {
78*4882a593Smuzhiyun				pins = "gpio_pwrctrl1";
79*4882a593Smuzhiyun				function = "pin_fun1";
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun			rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
83*4882a593Smuzhiyun				pins = "gpio_pwrctrl1";
84*4882a593Smuzhiyun				function = "pin_fun2";
85*4882a593Smuzhiyun			};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun			rk806_dvs1_rst: rk806_dvs1_rst {
88*4882a593Smuzhiyun				pins = "gpio_pwrctrl1";
89*4882a593Smuzhiyun				function = "pin_fun3";
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun			rk806_dvs2_null: rk806_dvs2_null {
93*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
94*4882a593Smuzhiyun				function = "pin_fun0";
95*4882a593Smuzhiyun			};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun			rk806_dvs2_slp: rk806_dvs2_slp {
98*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
99*4882a593Smuzhiyun				function = "pin_fun1";
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
103*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
104*4882a593Smuzhiyun				function = "pin_fun2";
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun			rk806_dvs2_rst: rk806_dvs2_rst {
108*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
109*4882a593Smuzhiyun				function = "pin_fun3";
110*4882a593Smuzhiyun			};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun			rk806_dvs2_dvs: rk806_dvs2_dvs {
113*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
114*4882a593Smuzhiyun				function = "pin_fun4";
115*4882a593Smuzhiyun			};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun			rk806_dvs2_gpio: rk806_dvs2_gpio {
118*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
119*4882a593Smuzhiyun				function = "pin_fun5";
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			rk806_dvs3_null: rk806_dvs3_null {
123*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
124*4882a593Smuzhiyun				function = "pin_fun0";
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun			rk806_dvs3_slp: rk806_dvs3_slp {
128*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
129*4882a593Smuzhiyun				function = "pin_fun1";
130*4882a593Smuzhiyun			};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun			rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
133*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
134*4882a593Smuzhiyun				function = "pin_fun2";
135*4882a593Smuzhiyun			};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun			rk806_dvs3_rst: rk806_dvs3_rst {
138*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
139*4882a593Smuzhiyun				function = "pin_fun3";
140*4882a593Smuzhiyun			};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun			rk806_dvs3_dvs: rk806_dvs3_dvs {
143*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
144*4882a593Smuzhiyun				function = "pin_fun4";
145*4882a593Smuzhiyun			};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun			rk806_dvs3_gpio: rk806_dvs3_gpio {
148*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
149*4882a593Smuzhiyun				function = "pin_fun5";
150*4882a593Smuzhiyun			};
151*4882a593Smuzhiyun		};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		regulators {
154*4882a593Smuzhiyun			vdd_gpu_s0: DCDC_REG1 {
155*4882a593Smuzhiyun				regulator-boot-on;
156*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
157*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
158*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
159*4882a593Smuzhiyun				regulator-enable-ramp-delay = <400>;
160*4882a593Smuzhiyun				regulator-name = "vdd_gpu_s0";
161*4882a593Smuzhiyun				regulator-state-mem {
162*4882a593Smuzhiyun					regulator-off-in-suspend;
163*4882a593Smuzhiyun				};
164*4882a593Smuzhiyun			};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun			vdd_npu_s0: DCDC_REG2 {
167*4882a593Smuzhiyun				regulator-always-on;
168*4882a593Smuzhiyun				regulator-boot-on;
169*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
170*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
171*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
172*4882a593Smuzhiyun				regulator-name = "vdd_npu_s0";
173*4882a593Smuzhiyun				regulator-state-mem {
174*4882a593Smuzhiyun					regulator-off-in-suspend;
175*4882a593Smuzhiyun				};
176*4882a593Smuzhiyun			};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun			vdd_log_s0: DCDC_REG3 {
179*4882a593Smuzhiyun				regulator-always-on;
180*4882a593Smuzhiyun				regulator-boot-on;
181*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
182*4882a593Smuzhiyun				regulator-max-microvolt = <750000>;
183*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
184*4882a593Smuzhiyun				regulator-name = "vdd_log_s0";
185*4882a593Smuzhiyun				regulator-state-mem {
186*4882a593Smuzhiyun					regulator-off-in-suspend;
187*4882a593Smuzhiyun					regulator-suspend-microvolt = <750000>;
188*4882a593Smuzhiyun				};
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			vdd_vdenc_s0: DCDC_REG4 {
192*4882a593Smuzhiyun				regulator-always-on;
193*4882a593Smuzhiyun				regulator-boot-on;
194*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
195*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
196*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
197*4882a593Smuzhiyun				regulator-name = "vdd_vdenc_s0";
198*4882a593Smuzhiyun				regulator-state-mem {
199*4882a593Smuzhiyun					regulator-off-in-suspend;
200*4882a593Smuzhiyun				};
201*4882a593Smuzhiyun			};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun			vdd_gpu_mem_s0: DCDC_REG5 {
204*4882a593Smuzhiyun				regulator-boot-on;
205*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
206*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
207*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
208*4882a593Smuzhiyun				regulator-enable-ramp-delay = <400>;
209*4882a593Smuzhiyun				regulator-name = "vdd_gpu_mem_s0";
210*4882a593Smuzhiyun				regulator-state-mem {
211*4882a593Smuzhiyun					regulator-off-in-suspend;
212*4882a593Smuzhiyun				};
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun			vdd_npu_mem_s0: DCDC_REG6 {
216*4882a593Smuzhiyun				regulator-always-on;
217*4882a593Smuzhiyun				regulator-boot-on;
218*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
219*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
220*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
221*4882a593Smuzhiyun				regulator-name = "vdd_npu_mem_s0";
222*4882a593Smuzhiyun				regulator-state-mem {
223*4882a593Smuzhiyun					regulator-off-in-suspend;
224*4882a593Smuzhiyun				};
225*4882a593Smuzhiyun			};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun			vcc_2v0_pldo_s3: DCDC_REG7 {
228*4882a593Smuzhiyun				regulator-always-on;
229*4882a593Smuzhiyun				regulator-boot-on;
230*4882a593Smuzhiyun				regulator-min-microvolt = <2000000>;
231*4882a593Smuzhiyun				regulator-max-microvolt = <2000000>;
232*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
233*4882a593Smuzhiyun				regulator-name = "vdd_2v0_pldo_s3";
234*4882a593Smuzhiyun				regulator-state-mem {
235*4882a593Smuzhiyun					regulator-on-in-suspend;
236*4882a593Smuzhiyun					regulator-suspend-microvolt = <2000000>;
237*4882a593Smuzhiyun				};
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			vdd_vdenc_mem_s0: DCDC_REG8 {
241*4882a593Smuzhiyun				regulator-always-on;
242*4882a593Smuzhiyun				regulator-boot-on;
243*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
244*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
245*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
246*4882a593Smuzhiyun				regulator-name = "vdd_vdenc_mem_s0";
247*4882a593Smuzhiyun				regulator-state-mem {
248*4882a593Smuzhiyun					regulator-off-in-suspend;
249*4882a593Smuzhiyun				};
250*4882a593Smuzhiyun			};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun			vdd2_ddr_s3: DCDC_REG9 {
253*4882a593Smuzhiyun				regulator-always-on;
254*4882a593Smuzhiyun				regulator-boot-on;
255*4882a593Smuzhiyun				regulator-name = "vdd2_ddr_s3";
256*4882a593Smuzhiyun				regulator-state-mem {
257*4882a593Smuzhiyun					regulator-on-in-suspend;
258*4882a593Smuzhiyun				};
259*4882a593Smuzhiyun			};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun			vcc_1v1_nldo_s3: DCDC_REG10 {
262*4882a593Smuzhiyun				regulator-always-on;
263*4882a593Smuzhiyun				regulator-boot-on;
264*4882a593Smuzhiyun				regulator-min-microvolt = <1100000>;
265*4882a593Smuzhiyun				regulator-max-microvolt = <1100000>;
266*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
267*4882a593Smuzhiyun				regulator-name = "vcc_1v1_nldo_s3";
268*4882a593Smuzhiyun				regulator-state-mem {
269*4882a593Smuzhiyun					regulator-on-in-suspend;
270*4882a593Smuzhiyun					regulator-suspend-microvolt = <1100000>;
271*4882a593Smuzhiyun				};
272*4882a593Smuzhiyun			};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun			avcc_1v8_s0: PLDO_REG1 {
275*4882a593Smuzhiyun				regulator-always-on;
276*4882a593Smuzhiyun				regulator-boot-on;
277*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
278*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
279*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
280*4882a593Smuzhiyun				regulator-name = "avcc_1v8_s0";
281*4882a593Smuzhiyun				regulator-state-mem {
282*4882a593Smuzhiyun					regulator-off-in-suspend;
283*4882a593Smuzhiyun				};
284*4882a593Smuzhiyun			};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun			vdd1_1v8_ddr_s3: PLDO_REG2 {
287*4882a593Smuzhiyun				regulator-always-on;
288*4882a593Smuzhiyun				regulator-boot-on;
289*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
290*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
291*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
292*4882a593Smuzhiyun				regulator-name = "vdd1_1v8_ddr_s3";
293*4882a593Smuzhiyun				regulator-state-mem {
294*4882a593Smuzhiyun					regulator-on-in-suspend;
295*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
296*4882a593Smuzhiyun				};
297*4882a593Smuzhiyun			};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun			vcc_1v8_s3: PLDO_REG3 {
300*4882a593Smuzhiyun				regulator-always-on;
301*4882a593Smuzhiyun				regulator-boot-on;
302*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
303*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
304*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
305*4882a593Smuzhiyun				regulator-name = "vcc_1v8_s3";
306*4882a593Smuzhiyun				regulator-state-mem {
307*4882a593Smuzhiyun					regulator-on-in-suspend;
308*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
309*4882a593Smuzhiyun				};
310*4882a593Smuzhiyun			};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun			vcc_3v3_s0: PLDO_REG4 {
313*4882a593Smuzhiyun				regulator-always-on;
314*4882a593Smuzhiyun				regulator-boot-on;
315*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
316*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
317*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
318*4882a593Smuzhiyun				regulator-name = "vcc_3v3_s0";
319*4882a593Smuzhiyun				regulator-state-mem {
320*4882a593Smuzhiyun					regulator-off-in-suspend;
321*4882a593Smuzhiyun				};
322*4882a593Smuzhiyun			};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun			vccio_sd_s0: PLDO_REG5 {
325*4882a593Smuzhiyun				regulator-always-on;
326*4882a593Smuzhiyun				regulator-boot-on;
327*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
328*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
329*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
330*4882a593Smuzhiyun				regulator-name = "vccio_sd_s0";
331*4882a593Smuzhiyun				regulator-state-mem {
332*4882a593Smuzhiyun					regulator-off-in-suspend;
333*4882a593Smuzhiyun				};
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun			master_pldo6_s3: PLDO_REG6 {
337*4882a593Smuzhiyun				regulator-always-on;
338*4882a593Smuzhiyun				regulator-boot-on;
339*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
340*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
341*4882a593Smuzhiyun				regulator-name = "master_pldo6_s3";
342*4882a593Smuzhiyun				regulator-state-mem {
343*4882a593Smuzhiyun					regulator-on-in-suspend;
344*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
345*4882a593Smuzhiyun				};
346*4882a593Smuzhiyun			};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun			vdd_0v75_s3: NLDO_REG1 {
349*4882a593Smuzhiyun				regulator-always-on;
350*4882a593Smuzhiyun				regulator-boot-on;
351*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
352*4882a593Smuzhiyun				regulator-max-microvolt = <750000>;
353*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
354*4882a593Smuzhiyun				regulator-name = "vdd_0v75_s3";
355*4882a593Smuzhiyun				regulator-state-mem {
356*4882a593Smuzhiyun					regulator-on-in-suspend;
357*4882a593Smuzhiyun					regulator-suspend-microvolt = <750000>;
358*4882a593Smuzhiyun				};
359*4882a593Smuzhiyun			};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun			vdd2l_0v9_ddr_s3: NLDO_REG2 {
362*4882a593Smuzhiyun				regulator-always-on;
363*4882a593Smuzhiyun				regulator-boot-on;
364*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
365*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
366*4882a593Smuzhiyun				regulator-name = "vdd2l_0v9_ddr_s3";
367*4882a593Smuzhiyun				regulator-state-mem {
368*4882a593Smuzhiyun					regulator-on-in-suspend;
369*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
370*4882a593Smuzhiyun				};
371*4882a593Smuzhiyun			};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun			master_nldo3: NLDO_REG3 {
374*4882a593Smuzhiyun				regulator-name = "master_nldo3";
375*4882a593Smuzhiyun				regulator-state-mem {
376*4882a593Smuzhiyun					regulator-off-in-suspend;
377*4882a593Smuzhiyun				};
378*4882a593Smuzhiyun			};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun			avdd_0v75_s0: NLDO_REG4 {
381*4882a593Smuzhiyun				regulator-always-on;
382*4882a593Smuzhiyun				regulator-boot-on;
383*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
384*4882a593Smuzhiyun				regulator-max-microvolt = <750000>;
385*4882a593Smuzhiyun				regulator-name = "avdd_0v75_s0";
386*4882a593Smuzhiyun				regulator-state-mem {
387*4882a593Smuzhiyun					regulator-off-in-suspend;
388*4882a593Smuzhiyun				};
389*4882a593Smuzhiyun			};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun			vdd_0v85_s0: NLDO_REG5 {
392*4882a593Smuzhiyun				regulator-always-on;
393*4882a593Smuzhiyun				regulator-boot-on;
394*4882a593Smuzhiyun				regulator-min-microvolt = <850000>;
395*4882a593Smuzhiyun				regulator-max-microvolt = <850000>;
396*4882a593Smuzhiyun				regulator-name = "vdd_0v85_s0";
397*4882a593Smuzhiyun				regulator-state-mem {
398*4882a593Smuzhiyun					regulator-off-in-suspend;
399*4882a593Smuzhiyun				};
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun	rk806slave: rk806slave@1 {
405*4882a593Smuzhiyun		compatible = "rockchip,rk806";
406*4882a593Smuzhiyun		spi-max-frequency = <1000000>;
407*4882a593Smuzhiyun		reg = <0x01>;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
410*4882a593Smuzhiyun		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep";
413*4882a593Smuzhiyun		pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
414*4882a593Smuzhiyun		pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun		/* 0: restart PMU;
417*4882a593Smuzhiyun		 * 1: reset all the power off reset registers,
418*4882a593Smuzhiyun		 *    forcing the state to switch to ACTIVE mode;
419*4882a593Smuzhiyun		 * 2: Reset all the power off reset registers,
420*4882a593Smuzhiyun		 *    forcing the state to switch to ACTIVE mode,
421*4882a593Smuzhiyun		 *    and simultaneously pull down the RESETB PIN for 5mS before releasing
422*4882a593Smuzhiyun		 */
423*4882a593Smuzhiyun		pmic-reset-func = <1>;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
426*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
427*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
428*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
429*4882a593Smuzhiyun		vcc5-supply = <&vcc5v0_sys>;
430*4882a593Smuzhiyun		vcc6-supply = <&vcc5v0_sys>;
431*4882a593Smuzhiyun		vcc7-supply = <&vcc5v0_sys>;
432*4882a593Smuzhiyun		vcc8-supply = <&vcc5v0_sys>;
433*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
434*4882a593Smuzhiyun		vcc10-supply = <&vcc5v0_sys>;
435*4882a593Smuzhiyun		vcc11-supply = <&vcc_2v0_pldo_s3>;
436*4882a593Smuzhiyun		vcc12-supply = <&vcc5v0_sys>;
437*4882a593Smuzhiyun		vcc13-supply = <&vcc_1v1_nldo_s3>;
438*4882a593Smuzhiyun		vcc14-supply = <&vcc_2v0_pldo_s3>;
439*4882a593Smuzhiyun		vcca-supply = <&vcc5v0_sys>;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun		pwrkey {
442*4882a593Smuzhiyun			status = "disabled";
443*4882a593Smuzhiyun		};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun		pinctrl_slave_rk806: pinctrl_slave_rk806 {
446*4882a593Smuzhiyun			gpio-controller;
447*4882a593Smuzhiyun			#gpio-cells = <2>;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun			rk806_slave_dvs1_null: rk806_slave_dvs1_null {
450*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
451*4882a593Smuzhiyun				function = "pin_fun0";
452*4882a593Smuzhiyun			};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun			rk806_slave_dvs1_slp: rk806_slave_dvs1_slp {
455*4882a593Smuzhiyun				pins = "gpio_pwrctrl1";
456*4882a593Smuzhiyun				function = "pin_fun1";
457*4882a593Smuzhiyun			};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun			rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn {
460*4882a593Smuzhiyun				pins = "gpio_pwrctrl1";
461*4882a593Smuzhiyun				function = "pin_fun2";
462*4882a593Smuzhiyun			};
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun			rk806_slave_dvs1_rst: rk806_slave_dvs1_rst {
465*4882a593Smuzhiyun				pins = "gpio_pwrctrl1";
466*4882a593Smuzhiyun				function = "pin_fun3";
467*4882a593Smuzhiyun			};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun			rk806_slave_dvs2_null: rk806_slave_dvs2_null {
470*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
471*4882a593Smuzhiyun				function = "pin_fun0";
472*4882a593Smuzhiyun			};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun			rk806_slave_dvs2_slp: rk806_slave_dvs2_slp {
475*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
476*4882a593Smuzhiyun				function = "pin_fun1";
477*4882a593Smuzhiyun			};
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun			rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn {
480*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
481*4882a593Smuzhiyun				function = "pin_fun2";
482*4882a593Smuzhiyun			};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun			rk806_slave_dvs2_rst: rk806_slave_dvs2_rst {
485*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
486*4882a593Smuzhiyun				function = "pin_fun3";
487*4882a593Smuzhiyun			};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun			rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs {
490*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
491*4882a593Smuzhiyun				function = "pin_fun4";
492*4882a593Smuzhiyun			};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun			rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio {
495*4882a593Smuzhiyun				pins = "gpio_pwrctrl2";
496*4882a593Smuzhiyun				function = "pin_fun5";
497*4882a593Smuzhiyun			};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun			rk806_slave_dvs3_null: rk806_slave_dvs3_null {
500*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
501*4882a593Smuzhiyun				function = "pin_fun0";
502*4882a593Smuzhiyun			};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun			rk806_slave_dvs3_slp: rk806_slave_dvs3_slp {
505*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
506*4882a593Smuzhiyun				function = "pin_fun1";
507*4882a593Smuzhiyun			};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun			rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn {
510*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
511*4882a593Smuzhiyun				function = "pin_fun2";
512*4882a593Smuzhiyun			};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun			rk806_slave_dvs3_rst: rk806_slave_dvs3_rst {
515*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
516*4882a593Smuzhiyun				function = "pin_fun3";
517*4882a593Smuzhiyun			};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun			rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs {
520*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
521*4882a593Smuzhiyun				function = "pin_fun4";
522*4882a593Smuzhiyun			};
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun			rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio {
525*4882a593Smuzhiyun				pins = "gpio_pwrctrl3";
526*4882a593Smuzhiyun				function = "pin_fun5";
527*4882a593Smuzhiyun			};
528*4882a593Smuzhiyun		};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun		regulators {
531*4882a593Smuzhiyun			vdd_cpu_big1_s0: DCDC_REG1 {
532*4882a593Smuzhiyun				regulator-always-on;
533*4882a593Smuzhiyun				regulator-boot-on;
534*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
535*4882a593Smuzhiyun				regulator-max-microvolt = <1050000>;
536*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
537*4882a593Smuzhiyun				regulator-name = "vdd_cpu_big1_s0";
538*4882a593Smuzhiyun				regulator-state-mem {
539*4882a593Smuzhiyun					regulator-off-in-suspend;
540*4882a593Smuzhiyun				};
541*4882a593Smuzhiyun			};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun			vdd_cpu_big0_s0: DCDC_REG2 {
544*4882a593Smuzhiyun				regulator-always-on;
545*4882a593Smuzhiyun				regulator-boot-on;
546*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
547*4882a593Smuzhiyun				regulator-max-microvolt = <1050000>;
548*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
549*4882a593Smuzhiyun				regulator-name = "vdd_cpu_big0_s0";
550*4882a593Smuzhiyun				regulator-state-mem {
551*4882a593Smuzhiyun					regulator-off-in-suspend;
552*4882a593Smuzhiyun				};
553*4882a593Smuzhiyun			};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun			vdd_cpu_lit_s0: DCDC_REG3 {
556*4882a593Smuzhiyun				regulator-always-on;
557*4882a593Smuzhiyun				regulator-boot-on;
558*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
559*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
560*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
561*4882a593Smuzhiyun				regulator-name = "vdd_cpu_lit_s0";
562*4882a593Smuzhiyun				regulator-state-mem {
563*4882a593Smuzhiyun					regulator-off-in-suspend;
564*4882a593Smuzhiyun				};
565*4882a593Smuzhiyun			};
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun			vcc_3v3_s3: DCDC_REG4 {
568*4882a593Smuzhiyun				regulator-always-on;
569*4882a593Smuzhiyun				regulator-boot-on;
570*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
571*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
572*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
573*4882a593Smuzhiyun				regulator-name = "vcc_3v3_s3";
574*4882a593Smuzhiyun				regulator-state-mem {
575*4882a593Smuzhiyun					regulator-on-in-suspend;
576*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
577*4882a593Smuzhiyun				};
578*4882a593Smuzhiyun			};
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun			vdd_cpu_big1_mem_s0: DCDC_REG5 {
581*4882a593Smuzhiyun				regulator-always-on;
582*4882a593Smuzhiyun				regulator-boot-on;
583*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
584*4882a593Smuzhiyun				regulator-max-microvolt = <1050000>;
585*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
586*4882a593Smuzhiyun				regulator-name = "vdd_cpu_big1_mem_s0";
587*4882a593Smuzhiyun				regulator-state-mem {
588*4882a593Smuzhiyun					regulator-off-in-suspend;
589*4882a593Smuzhiyun				};
590*4882a593Smuzhiyun			};
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun			vdd_cpu_big0_mem_s0: DCDC_REG6 {
594*4882a593Smuzhiyun				regulator-always-on;
595*4882a593Smuzhiyun				regulator-boot-on;
596*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
597*4882a593Smuzhiyun				regulator-max-microvolt = <1050000>;
598*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
599*4882a593Smuzhiyun				regulator-name = "vdd_cpu_big0_mem_s0";
600*4882a593Smuzhiyun				regulator-state-mem {
601*4882a593Smuzhiyun					regulator-off-in-suspend;
602*4882a593Smuzhiyun				};
603*4882a593Smuzhiyun			};
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun			vcc_1v8_s0: DCDC_REG7 {
606*4882a593Smuzhiyun				regulator-always-on;
607*4882a593Smuzhiyun				regulator-boot-on;
608*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
609*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
610*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
611*4882a593Smuzhiyun				regulator-name = "vcc_1v8_s0";
612*4882a593Smuzhiyun				regulator-state-mem {
613*4882a593Smuzhiyun					regulator-off-in-suspend;
614*4882a593Smuzhiyun				};
615*4882a593Smuzhiyun			};
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun			vdd_cpu_lit_mem_s0: DCDC_REG8 {
618*4882a593Smuzhiyun				regulator-always-on;
619*4882a593Smuzhiyun				regulator-boot-on;
620*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
621*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
622*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
623*4882a593Smuzhiyun				regulator-name = "vdd_cpu_lit_mem_s0";
624*4882a593Smuzhiyun				regulator-state-mem {
625*4882a593Smuzhiyun					regulator-off-in-suspend;
626*4882a593Smuzhiyun				};
627*4882a593Smuzhiyun			};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun			vddq_ddr_s0: DCDC_REG9 {
630*4882a593Smuzhiyun				regulator-always-on;
631*4882a593Smuzhiyun				regulator-boot-on;
632*4882a593Smuzhiyun				regulator-name = "vddq_ddr_s0";
633*4882a593Smuzhiyun				regulator-state-mem {
634*4882a593Smuzhiyun					regulator-off-in-suspend;
635*4882a593Smuzhiyun				};
636*4882a593Smuzhiyun			};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun			vdd_ddr_s0: DCDC_REG10 {
639*4882a593Smuzhiyun				regulator-always-on;
640*4882a593Smuzhiyun				regulator-boot-on;
641*4882a593Smuzhiyun				regulator-min-microvolt = <675000>;
642*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
643*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
644*4882a593Smuzhiyun				regulator-name = "vdd_ddr_s0";
645*4882a593Smuzhiyun				regulator-state-mem {
646*4882a593Smuzhiyun					regulator-off-in-suspend;
647*4882a593Smuzhiyun				};
648*4882a593Smuzhiyun			};
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun			vcc_1v8_cam_s0: PLDO_REG1 {
651*4882a593Smuzhiyun				regulator-always-on;
652*4882a593Smuzhiyun				regulator-boot-on;
653*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
654*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
655*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
656*4882a593Smuzhiyun				regulator-name = "vcc_1v8_cam_s0";
657*4882a593Smuzhiyun				regulator-state-mem {
658*4882a593Smuzhiyun					regulator-off-in-suspend;
659*4882a593Smuzhiyun				};
660*4882a593Smuzhiyun			};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun			avdd1v8_ddr_pll_s0: PLDO_REG2 {
663*4882a593Smuzhiyun				regulator-always-on;
664*4882a593Smuzhiyun				regulator-boot-on;
665*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
666*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
667*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
668*4882a593Smuzhiyun				regulator-name = "avdd1v8_ddr_pll_s0";
669*4882a593Smuzhiyun				regulator-state-mem {
670*4882a593Smuzhiyun					regulator-off-in-suspend;
671*4882a593Smuzhiyun				};
672*4882a593Smuzhiyun			};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun			vdd_1v8_pll_s0: PLDO_REG3 {
675*4882a593Smuzhiyun				regulator-always-on;
676*4882a593Smuzhiyun				regulator-boot-on;
677*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
678*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
679*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
680*4882a593Smuzhiyun				regulator-name = "vdd_1v8_pll_s0";
681*4882a593Smuzhiyun				regulator-state-mem {
682*4882a593Smuzhiyun					regulator-off-in-suspend;
683*4882a593Smuzhiyun				};
684*4882a593Smuzhiyun			};
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun			vcc_3v3_sd_s0: PLDO_REG4 {
687*4882a593Smuzhiyun				regulator-always-on;
688*4882a593Smuzhiyun				regulator-boot-on;
689*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
690*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
691*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
692*4882a593Smuzhiyun				regulator-name = "vcc_3v3_sd_s0";
693*4882a593Smuzhiyun				regulator-state-mem {
694*4882a593Smuzhiyun					regulator-off-in-suspend;
695*4882a593Smuzhiyun				};
696*4882a593Smuzhiyun			};
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun			vcc_2v8_cam_s0: PLDO_REG5 {
699*4882a593Smuzhiyun				regulator-always-on;
700*4882a593Smuzhiyun				regulator-boot-on;
701*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
702*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
703*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
704*4882a593Smuzhiyun				regulator-name = "vcc_2v8_cam_s0";
705*4882a593Smuzhiyun				regulator-state-mem {
706*4882a593Smuzhiyun					regulator-off-in-suspend;
707*4882a593Smuzhiyun				};
708*4882a593Smuzhiyun			};
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun			pldo6_s3: PLDO_REG6 {
711*4882a593Smuzhiyun				regulator-always-on;
712*4882a593Smuzhiyun				regulator-boot-on;
713*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
714*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
715*4882a593Smuzhiyun				regulator-name = "pldo6_s3";
716*4882a593Smuzhiyun				regulator-state-mem {
717*4882a593Smuzhiyun					regulator-on-in-suspend;
718*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
719*4882a593Smuzhiyun				};
720*4882a593Smuzhiyun			};
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun			vdd_0v75_pll_s0: NLDO_REG1 {
723*4882a593Smuzhiyun				regulator-always-on;
724*4882a593Smuzhiyun				regulator-boot-on;
725*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
726*4882a593Smuzhiyun				regulator-max-microvolt = <750000>;
727*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
728*4882a593Smuzhiyun				regulator-name = "vdd_0v75_pll_s0";
729*4882a593Smuzhiyun				regulator-state-mem {
730*4882a593Smuzhiyun					regulator-off-in-suspend;
731*4882a593Smuzhiyun				};
732*4882a593Smuzhiyun			};
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun			vdd_ddr_pll_s0: NLDO_REG2 {
735*4882a593Smuzhiyun				regulator-always-on;
736*4882a593Smuzhiyun				regulator-boot-on;
737*4882a593Smuzhiyun				regulator-min-microvolt = <850000>;
738*4882a593Smuzhiyun				regulator-max-microvolt = <850000>;
739*4882a593Smuzhiyun				regulator-name = "vdd_ddr_pll_s0";
740*4882a593Smuzhiyun				regulator-state-mem {
741*4882a593Smuzhiyun					regulator-off-in-suspend;
742*4882a593Smuzhiyun				};
743*4882a593Smuzhiyun			};
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun			slave_nldo3: NLDO_REG3 {
746*4882a593Smuzhiyun				regulator-name = "slave_nldo3";
747*4882a593Smuzhiyun				regulator-state-mem {
748*4882a593Smuzhiyun					regulator-off-in-suspend;
749*4882a593Smuzhiyun				};
750*4882a593Smuzhiyun			};
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun			avdd_1v2_cam_s0: NLDO_REG4 {
753*4882a593Smuzhiyun				regulator-always-on;
754*4882a593Smuzhiyun				regulator-boot-on;
755*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
756*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
757*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
758*4882a593Smuzhiyun				regulator-name = "avdd_1v2_cam_s0";
759*4882a593Smuzhiyun				regulator-state-mem {
760*4882a593Smuzhiyun					regulator-off-in-suspend;
761*4882a593Smuzhiyun				};
762*4882a593Smuzhiyun			};
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun			avdd_1v2_s0: NLDO_REG5 {
765*4882a593Smuzhiyun				regulator-always-on;
766*4882a593Smuzhiyun				regulator-boot-on;
767*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
768*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
769*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
770*4882a593Smuzhiyun				regulator-name = "avdd_1v2_s0";
771*4882a593Smuzhiyun				regulator-state-mem {
772*4882a593Smuzhiyun					regulator-off-in-suspend;
773*4882a593Smuzhiyun				};
774*4882a593Smuzhiyun			};
775*4882a593Smuzhiyun		};
776*4882a593Smuzhiyun	};
777*4882a593Smuzhiyun};
778