xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
8*4882a593Smuzhiyun#include "rk3588s.dtsi"
9*4882a593Smuzhiyun#include "rk3588s-evb.dtsi"
10*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	combophy_avdd0v85: combophy-avdd0v85 {
14*4882a593Smuzhiyun		compatible = "regulator-fixed";
15*4882a593Smuzhiyun		regulator-name = "combophy_avdd0v85";
16*4882a593Smuzhiyun		regulator-boot-on;
17*4882a593Smuzhiyun		regulator-always-on;
18*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
19*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
20*4882a593Smuzhiyun		vin-supply = <&vdd_0v85_s0>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	combophy_avdd1v8: combophy-avdd1v8 {
24*4882a593Smuzhiyun		compatible = "regulator-fixed";
25*4882a593Smuzhiyun		regulator-name = "combophy_avdd1v8";
26*4882a593Smuzhiyun		regulator-boot-on;
27*4882a593Smuzhiyun		regulator-always-on;
28*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
29*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
30*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	es7202_sound_micarray: es7202-sound-micarray {
34*4882a593Smuzhiyun		status = "okay";
35*4882a593Smuzhiyun		compatible = "simple-audio-card";
36*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
37*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,sound-micarray";
38*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
39*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
40*4882a593Smuzhiyun			format = "pdm";
41*4882a593Smuzhiyun			cpu {
42*4882a593Smuzhiyun				sound-dai = <&pdm0>;
43*4882a593Smuzhiyun			};
44*4882a593Smuzhiyun			codec {
45*4882a593Smuzhiyun				sound-dai = <&es7202>;
46*4882a593Smuzhiyun			};
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	es8388_sound: es8388-sound {
51*4882a593Smuzhiyun		status = "okay";
52*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
53*4882a593Smuzhiyun		rockchip,card-name = "rockchip-es8388";
54*4882a593Smuzhiyun		hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
55*4882a593Smuzhiyun		io-channels = <&saradc 3>;
56*4882a593Smuzhiyun		io-channel-names = "adc-detect";
57*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
58*4882a593Smuzhiyun		poll-interval = <100>;
59*4882a593Smuzhiyun		spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun		hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
61*4882a593Smuzhiyun		rockchip,format = "i2s";
62*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
63*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
64*4882a593Smuzhiyun		rockchip,codec = <&es8388>;
65*4882a593Smuzhiyun		rockchip,audio-routing =
66*4882a593Smuzhiyun			"Headphone", "LOUT1",
67*4882a593Smuzhiyun			"Headphone", "ROUT1",
68*4882a593Smuzhiyun			"Speaker", "LOUT2",
69*4882a593Smuzhiyun			"Speaker", "ROUT2",
70*4882a593Smuzhiyun			"Headphone", "Headphone Power",
71*4882a593Smuzhiyun			"Headphone", "Headphone Power",
72*4882a593Smuzhiyun			"Speaker", "Speaker Power",
73*4882a593Smuzhiyun			"Speaker", "Speaker Power",
74*4882a593Smuzhiyun			"LINPUT1", "Main Mic",
75*4882a593Smuzhiyun			"LINPUT2", "Main Mic",
76*4882a593Smuzhiyun			"RINPUT1", "Headset Mic",
77*4882a593Smuzhiyun			"RINPUT2", "Headset Mic";
78*4882a593Smuzhiyun		pinctrl-names = "default";
79*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
80*4882a593Smuzhiyun		play-pause-key {
81*4882a593Smuzhiyun			label = "playpause";
82*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
83*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	fan: pwm-fan {
88*4882a593Smuzhiyun		compatible = "pwm-fan";
89*4882a593Smuzhiyun		#cooling-cells = <2>;
90*4882a593Smuzhiyun		pwms = <&pwm11 0 50000 0>;
91*4882a593Smuzhiyun		cooling-levels = <0 50 100 150 200 255>;
92*4882a593Smuzhiyun		rockchip,temp-trips = <
93*4882a593Smuzhiyun			50000	1
94*4882a593Smuzhiyun			55000	2
95*4882a593Smuzhiyun			60000	3
96*4882a593Smuzhiyun			65000	4
97*4882a593Smuzhiyun			70000	5
98*4882a593Smuzhiyun		>;
99*4882a593Smuzhiyun	};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun	vbus5v0_typec: vbus5v0-typec {
102*4882a593Smuzhiyun		compatible = "regulator-fixed";
103*4882a593Smuzhiyun		regulator-name = "vbus5v0_typec";
104*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
105*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
106*4882a593Smuzhiyun		enable-active-high;
107*4882a593Smuzhiyun		gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
108*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
109*4882a593Smuzhiyun		pinctrl-names = "default";
110*4882a593Smuzhiyun		pinctrl-0 = <&typec5v_pwren>;
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	vcc3v3_lcd_n: vcc3v3-lcd0-n {
114*4882a593Smuzhiyun		compatible = "regulator-fixed";
115*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd0_n";
116*4882a593Smuzhiyun		regulator-boot-on;
117*4882a593Smuzhiyun		enable-active-high;
118*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
119*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s0>;
120*4882a593Smuzhiyun	};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun	vcc3v3_pcie20: vcc3v3-pcie20 {
123*4882a593Smuzhiyun		compatible = "regulator-fixed";
124*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie20";
125*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
126*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
127*4882a593Smuzhiyun		enable-active-high;
128*4882a593Smuzhiyun		gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
129*4882a593Smuzhiyun		startup-delay-us = <5000>;
130*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
134*4882a593Smuzhiyun		compatible = "regulator-fixed";
135*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
136*4882a593Smuzhiyun		regulator-boot-on;
137*4882a593Smuzhiyun		regulator-always-on;
138*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
139*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
140*4882a593Smuzhiyun		enable-active-high;
141*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
142*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
143*4882a593Smuzhiyun		pinctrl-names = "default";
144*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
148*4882a593Smuzhiyun		compatible = "regulator-fixed";
149*4882a593Smuzhiyun		regulator-name = "vcc_1v1_nldo_s3";
150*4882a593Smuzhiyun		regulator-always-on;
151*4882a593Smuzhiyun		regulator-boot-on;
152*4882a593Smuzhiyun		regulator-min-microvolt = <1100000>;
153*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
154*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
155*4882a593Smuzhiyun	};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	vcc_1v2_cam_s0: vcc-1v2-cam-s0 {
158*4882a593Smuzhiyun		compatible = "regulator-fixed";
159*4882a593Smuzhiyun		regulator-name = "vcc_1v2_cam_s0";
160*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
161*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
162*4882a593Smuzhiyun		gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
163*4882a593Smuzhiyun		enable-active-high;
164*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
165*4882a593Smuzhiyun		regulator-state-mem {
166*4882a593Smuzhiyun			regulator-off-in-suspend;
167*4882a593Smuzhiyun		};
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun	vcc_1v8_cam_s0: vcc-1v8-cam-s0 {
171*4882a593Smuzhiyun		compatible = "regulator-fixed";
172*4882a593Smuzhiyun		regulator-name = "vcc_1v8_cam_s0";
173*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
174*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
175*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	vcc_2v8_cam_s0: vcc-2v8-cam-s0 {
179*4882a593Smuzhiyun		compatible = "regulator-fixed";
180*4882a593Smuzhiyun		regulator-name = "vcc_2v8_cam_s0";
181*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
182*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
183*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun	vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
187*4882a593Smuzhiyun		compatible = "regulator-fixed";
188*4882a593Smuzhiyun		regulator-name = "vcc_3v3_sd_s0";
189*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
190*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
191*4882a593Smuzhiyun		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
192*4882a593Smuzhiyun		enable-active-low;
193*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
194*4882a593Smuzhiyun			regulator-state-mem {
195*4882a593Smuzhiyun			regulator-off-in-suspend;
196*4882a593Smuzhiyun		};
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
200*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
201*4882a593Smuzhiyun		clocks = <&hym8563>;
202*4882a593Smuzhiyun		clock-names = "ext_clock";
203*4882a593Smuzhiyun		uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
204*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
205*4882a593Smuzhiyun		pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>;
206*4882a593Smuzhiyun		pinctrl-1 = <&uart8_gpios>;
207*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
208*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
209*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
210*4882a593Smuzhiyun		status = "okay";
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
214*4882a593Smuzhiyun		compatible = "wlan-platdata";
215*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
216*4882a593Smuzhiyun		pinctrl-names = "default";
217*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
218*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
219*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
220*4882a593Smuzhiyun		status = "okay";
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&backlight {
225*4882a593Smuzhiyun	pwms = <&pwm13 0 25000 0>;
226*4882a593Smuzhiyun	status = "okay";
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&combphy0_ps {
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&combphy2_psu {
234*4882a593Smuzhiyun	status = "okay";
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun&dp0 {
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&dp0_in_vp2 {
242*4882a593Smuzhiyun	status = "okay";
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun/*
246*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled
247*4882a593Smuzhiyun * when dsi0 is enabled
248*4882a593Smuzhiyun */
249*4882a593Smuzhiyun&dsi0 {
250*4882a593Smuzhiyun	status = "okay";
251*4882a593Smuzhiyun};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun&dsi0_in_vp2 {
254*4882a593Smuzhiyun	status = "disabled";
255*4882a593Smuzhiyun};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun&dsi0_in_vp3 {
258*4882a593Smuzhiyun	status = "okay";
259*4882a593Smuzhiyun};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun&dsi0_panel {
262*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
263*4882a593Smuzhiyun	reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
264*4882a593Smuzhiyun	pinctrl-names = "default";
265*4882a593Smuzhiyun	pinctrl-0 = <&lcd_rst_gpio>;
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun/*
269*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled
270*4882a593Smuzhiyun * when dsi1 is enabled
271*4882a593Smuzhiyun */
272*4882a593Smuzhiyun&dsi1 {
273*4882a593Smuzhiyun	//rockchip,lane-rate = <650>;
274*4882a593Smuzhiyun	pinctrl-names = "default";
275*4882a593Smuzhiyun	pinctrl-0 = <&mipi_te1>;
276*4882a593Smuzhiyun	status = "disabled";
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun&dsi1_in_vp2 {
280*4882a593Smuzhiyun	status = "disabled";
281*4882a593Smuzhiyun};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun&dsi1_in_vp3 {
284*4882a593Smuzhiyun	status = "disabled";
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&dsi1_panel {
288*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
289*4882a593Smuzhiyun	compressed-data;
290*4882a593Smuzhiyun	/*
291*4882a593Smuzhiyun	 * because in hardware, the two screens share the reset pin,
292*4882a593Smuzhiyun	 * so reset-gpios need only in dsi1 enable and dsi0 disabled
293*4882a593Smuzhiyun	 * case.
294*4882a593Smuzhiyun	 */
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	//reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
297*4882a593Smuzhiyun	//pinctrl-names = "default";
298*4882a593Smuzhiyun	//pinctrl-0 = <&lcd_rst_gpio>;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun	dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun	slice-width = <720>;
303*4882a593Smuzhiyun	slice-height = <65>;
304*4882a593Smuzhiyun	version-major = <1>;
305*4882a593Smuzhiyun	version-minor = <1>;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun	panel-init-sequence = [
308*4882a593Smuzhiyun		29 10 03 f0 5a 5a
309*4882a593Smuzhiyun		/* Dsc Setting */
310*4882a593Smuzhiyun		/* Compression Enable */
311*4882a593Smuzhiyun		07 10 01 01
312*4882a593Smuzhiyun		/* Scaler Disable */
313*4882a593Smuzhiyun		15 10 02 c3 00
314*4882a593Smuzhiyun		/* PPS Setting */
315*4882a593Smuzhiyun		0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00
316*4882a593Smuzhiyun		29 10 03 f0 a5 a5
317*4882a593Smuzhiyun		/** Sleep Out */
318*4882a593Smuzhiyun		05 00 01 11
319*4882a593Smuzhiyun		/* 4. Common Setting */
320*4882a593Smuzhiyun		/* 4.1 TE(Vync) ON/OFF */
321*4882a593Smuzhiyun		15 00 02 35 00
322*4882a593Smuzhiyun		/* 4.2 CASET/PASET Setting */
323*4882a593Smuzhiyun		39 00 05 2a 00 00 05 9F
324*4882a593Smuzhiyun		39 00 05 2b 00 00 0c 2f
325*4882a593Smuzhiyun		/* 4.3 TSP SYNC Setting */
326*4882a593Smuzhiyun		39 00 03 f0 5a 5a
327*4882a593Smuzhiyun		39 00 0a B9 01 c0 3c 0b 00 00 00 11 03
328*4882a593Smuzhiyun		39 00 03 f0 a5 a5
329*4882a593Smuzhiyun		/* FD(Fast Discharge) Setting */
330*4882a593Smuzhiyun		39 00 03 f0 5a 5a
331*4882a593Smuzhiyun		15 00 02 b0 45
332*4882a593Smuzhiyun		15 00 02 b5 48
333*4882a593Smuzhiyun		39 00 03 f0 a5 a5
334*4882a593Smuzhiyun		/* 4.6 FFC Setting (MIPI CLK 529MHz) */
335*4882a593Smuzhiyun		39 00 03 f0 5a 5a
336*4882a593Smuzhiyun		39 00 03 fc 5a 5a
337*4882a593Smuzhiyun		15 00 02 b0 1E
338*4882a593Smuzhiyun		39 00 06 c5 09 10 b4 24 fb
339*4882a593Smuzhiyun		39 00 03 f0 a5 a5
340*4882a593Smuzhiyun		39 00 03 fc a5 a5
341*4882a593Smuzhiyun		/* OSC Spread Setting */
342*4882a593Smuzhiyun		39 00 03 f0 5a 5a
343*4882a593Smuzhiyun		39 00 03 fc 5a 5a
344*4882a593Smuzhiyun		15 00 02 b0 37
345*4882a593Smuzhiyun		/* FFC Setting; 0x04 : Disable */
346*4882a593Smuzhiyun		39 00 06 c5 04 ff 00 01 64
347*4882a593Smuzhiyun		39 00 03 f0 a5 a5
348*4882a593Smuzhiyun		39 00 03 fc a5 a5
349*4882a593Smuzhiyun		/* Dither IP Setting */
350*4882a593Smuzhiyun		39 00 03 FC 5A 5A
351*4882a593Smuzhiyun		15 00 02 b0 86
352*4882a593Smuzhiyun		15 00 02 eb 01
353*4882a593Smuzhiyun		39 00 03 FC a5 a5
354*4882a593Smuzhiyun		/* 5 Brightness Control */
355*4882a593Smuzhiyun		/* 5.1 Dimming Setting */
356*4882a593Smuzhiyun		39 10 03 f0 5a 5a
357*4882a593Smuzhiyun		15 10 02 b0 05
358*4882a593Smuzhiyun		15 10 02 b1 01
359*4882a593Smuzhiyun		15 10 02 b0 02
360*4882a593Smuzhiyun		15 10 02 b5 d3
361*4882a593Smuzhiyun		15 10 02 53 20
362*4882a593Smuzhiyun		39 10 03 f0 a5 a5
363*4882a593Smuzhiyun		39 10 03 51 02 ff
364*4882a593Smuzhiyun		05 32 01 29
365*4882a593Smuzhiyun	];
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun	panel-exit-sequence = [
368*4882a593Smuzhiyun		/* Display off */
369*4882a593Smuzhiyun		05 14 01 28
370*4882a593Smuzhiyun		/* Sleep In */
371*4882a593Smuzhiyun		05 00 01 10
372*4882a593Smuzhiyun		/* VCI stabilization setting */
373*4882a593Smuzhiyun		39 00 03 f0 5a 5a
374*4882a593Smuzhiyun		15 00 02 b0 05
375*4882a593Smuzhiyun		15 00 02 f4 01
376*4882a593Smuzhiyun		39 a0 03 f0 a5 a5
377*4882a593Smuzhiyun	];
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun	disp_timings1: display-timings {
380*4882a593Smuzhiyun		native-mode = <&dsi1_timing0>;
381*4882a593Smuzhiyun		dsi1_timing0: timing0 {
382*4882a593Smuzhiyun			clock-frequency = <280000000>;
383*4882a593Smuzhiyun			hactive = <1140>;
384*4882a593Smuzhiyun			vactive = <3120>;
385*4882a593Smuzhiyun			hfront-porch = <16>;
386*4882a593Smuzhiyun			hsync-len = <8>;
387*4882a593Smuzhiyun			hback-porch = <8>;
388*4882a593Smuzhiyun			vfront-porch = <4>;
389*4882a593Smuzhiyun			vsync-len = <2>;
390*4882a593Smuzhiyun			vback-porch = <16>;
391*4882a593Smuzhiyun			hsync-active = <0>;
392*4882a593Smuzhiyun			vsync-active = <0>;
393*4882a593Smuzhiyun			de-active = <0>;
394*4882a593Smuzhiyun			pixelclk-active = <0>;
395*4882a593Smuzhiyun		};
396*4882a593Smuzhiyun	};
397*4882a593Smuzhiyun};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun&i2c0 {
400*4882a593Smuzhiyun	status = "okay";
401*4882a593Smuzhiyun	pinctrl-names = "default";
402*4882a593Smuzhiyun	pinctrl-0 = <&i2c0m2_xfer>;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
405*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
406*4882a593Smuzhiyun		reg = <0x42>;
407*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
408*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
409*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big0_s0";
410*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
411*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
412*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
413*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
414*4882a593Smuzhiyun		regulator-boot-on;
415*4882a593Smuzhiyun		regulator-always-on;
416*4882a593Smuzhiyun		regulator-state-mem {
417*4882a593Smuzhiyun			regulator-off-in-suspend;
418*4882a593Smuzhiyun		};
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
422*4882a593Smuzhiyun		compatible = "rockchip,rk8603";
423*4882a593Smuzhiyun		reg = <0x43>;
424*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
425*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
426*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big1_s0";
427*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
428*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
429*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
430*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
431*4882a593Smuzhiyun		regulator-boot-on;
432*4882a593Smuzhiyun		regulator-always-on;
433*4882a593Smuzhiyun		regulator-state-mem {
434*4882a593Smuzhiyun			regulator-off-in-suspend;
435*4882a593Smuzhiyun		};
436*4882a593Smuzhiyun	};
437*4882a593Smuzhiyun};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun&i2c2 {
440*4882a593Smuzhiyun	status = "okay";
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun	vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
443*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
444*4882a593Smuzhiyun		reg = <0x42>;
445*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
446*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
447*4882a593Smuzhiyun		regulator-name = "vdd_npu_s0";
448*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
449*4882a593Smuzhiyun		regulator-max-microvolt = <950000>;
450*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
451*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
452*4882a593Smuzhiyun		regulator-boot-on;
453*4882a593Smuzhiyun		regulator-always-on;
454*4882a593Smuzhiyun		regulator-state-mem {
455*4882a593Smuzhiyun			regulator-off-in-suspend;
456*4882a593Smuzhiyun		};
457*4882a593Smuzhiyun	};
458*4882a593Smuzhiyun};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun&i2c3 {
461*4882a593Smuzhiyun	status = "okay";
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun	es8388: es8388@11 {
464*4882a593Smuzhiyun		status = "okay";
465*4882a593Smuzhiyun		#sound-dai-cells = <0>;
466*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
467*4882a593Smuzhiyun		reg = <0x11>;
468*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
469*4882a593Smuzhiyun		clock-names = "mclk";
470*4882a593Smuzhiyun		pinctrl-names = "default";
471*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
472*4882a593Smuzhiyun	};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun	es7202: es7202@32 {
475*4882a593Smuzhiyun		status = "okay";
476*4882a593Smuzhiyun		#sound-dai-cells = <0>;
477*4882a593Smuzhiyun		compatible = "ES7202_PDM_ADC_1";
478*4882a593Smuzhiyun		power-supply = <&vcc_1v8_s0>;	/* only 1v8 or 3v3, default is 3v3 */
479*4882a593Smuzhiyun		reg = <0x32>;
480*4882a593Smuzhiyun	};
481*4882a593Smuzhiyun};
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun&i2c4 {
484*4882a593Smuzhiyun	status = "okay";
485*4882a593Smuzhiyun	pinctrl-names = "default";
486*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m3_xfer>;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun	gt1x: gt1x@14 {
489*4882a593Smuzhiyun		compatible = "goodix,gt1x";
490*4882a593Smuzhiyun		reg = <0x14>;
491*4882a593Smuzhiyun		pinctrl-names = "default";
492*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
493*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
494*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
495*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
496*4882a593Smuzhiyun	};
497*4882a593Smuzhiyun};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun&i2c5 {
500*4882a593Smuzhiyun	status = "okay";
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun	ls_stk3332: light@47 {
503*4882a593Smuzhiyun		compatible = "ls_stk3332";
504*4882a593Smuzhiyun		status = "disabled";
505*4882a593Smuzhiyun		reg = <0x47>;
506*4882a593Smuzhiyun		type = <SENSOR_TYPE_LIGHT>;
507*4882a593Smuzhiyun		irq_enable = <0>;
508*4882a593Smuzhiyun		als_threshold_high = <100>;
509*4882a593Smuzhiyun		als_threshold_low = <10>;
510*4882a593Smuzhiyun		als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */
511*4882a593Smuzhiyun		poll_delay_ms = <100>;
512*4882a593Smuzhiyun	};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun	ps_stk3332: proximity@47 {
515*4882a593Smuzhiyun		compatible = "ps_stk3332";
516*4882a593Smuzhiyun		status = "disabled";
517*4882a593Smuzhiyun		reg = <0x47>;
518*4882a593Smuzhiyun		type = <SENSOR_TYPE_PROXIMITY>;
519*4882a593Smuzhiyun		//pinctrl-names = "default";
520*4882a593Smuzhiyun		//pinctrl-0 = <&gpio3_c6>;
521*4882a593Smuzhiyun		//irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
522*4882a593Smuzhiyun		//irq_enable = <1>;
523*4882a593Smuzhiyun		ps_threshold_high = <0x200>;
524*4882a593Smuzhiyun		ps_threshold_low = <0x100>;
525*4882a593Smuzhiyun		ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */
526*4882a593Smuzhiyun		ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/
527*4882a593Smuzhiyun		poll_delay_ms = <100>;
528*4882a593Smuzhiyun	};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun	mpu6500_acc: mpu_acc@68 {
531*4882a593Smuzhiyun		compatible = "mpu6500_acc";
532*4882a593Smuzhiyun		reg = <0x68>;
533*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>;
534*4882a593Smuzhiyun		irq_enable = <0>;
535*4882a593Smuzhiyun		poll_delay_ms = <30>;
536*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
537*4882a593Smuzhiyun		layout = <8>;
538*4882a593Smuzhiyun	};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun	mpu6500_gyro: mpu_gyro@68 {
541*4882a593Smuzhiyun		compatible = "mpu6500_gyro";
542*4882a593Smuzhiyun		reg = <0x68>;
543*4882a593Smuzhiyun		irq_enable = <0>;
544*4882a593Smuzhiyun		poll_delay_ms = <30>;
545*4882a593Smuzhiyun		type = <SENSOR_TYPE_GYROSCOPE>;
546*4882a593Smuzhiyun		layout = <8>;
547*4882a593Smuzhiyun	};
548*4882a593Smuzhiyun};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun&i2c8 {
551*4882a593Smuzhiyun	status = "okay";
552*4882a593Smuzhiyun	pinctrl-names = "default";
553*4882a593Smuzhiyun	pinctrl-0 = <&i2c8m2_xfer>;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun	usbc0: fusb302@22 {
556*4882a593Smuzhiyun		compatible = "fcs,fusb302";
557*4882a593Smuzhiyun		reg = <0x22>;
558*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
559*4882a593Smuzhiyun		interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
560*4882a593Smuzhiyun		pinctrl-names = "default";
561*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
562*4882a593Smuzhiyun		vbus-supply = <&vbus5v0_typec>;
563*4882a593Smuzhiyun		status = "okay";
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun		ports {
566*4882a593Smuzhiyun			#address-cells = <1>;
567*4882a593Smuzhiyun			#size-cells = <0>;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun			port@0 {
570*4882a593Smuzhiyun				reg = <0>;
571*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
572*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
573*4882a593Smuzhiyun				};
574*4882a593Smuzhiyun			};
575*4882a593Smuzhiyun		};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun		usb_con: connector {
578*4882a593Smuzhiyun			compatible = "usb-c-connector";
579*4882a593Smuzhiyun			label = "USB-C";
580*4882a593Smuzhiyun			data-role = "dual";
581*4882a593Smuzhiyun			power-role = "dual";
582*4882a593Smuzhiyun			try-power-role = "sink";
583*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
584*4882a593Smuzhiyun			sink-pdos =
585*4882a593Smuzhiyun				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
586*4882a593Smuzhiyun			source-pdos =
587*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun			altmodes {
590*4882a593Smuzhiyun				#address-cells = <1>;
591*4882a593Smuzhiyun				#size-cells = <0>;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun				altmode@0 {
594*4882a593Smuzhiyun					reg = <0>;
595*4882a593Smuzhiyun					svid = <0xff01>;
596*4882a593Smuzhiyun					vdo = <0xffffffff>;
597*4882a593Smuzhiyun				};
598*4882a593Smuzhiyun			};
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun			ports {
601*4882a593Smuzhiyun				#address-cells = <1>;
602*4882a593Smuzhiyun				#size-cells = <0>;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun				port@0 {
605*4882a593Smuzhiyun					reg = <0>;
606*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
607*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_orientation_switch>;
608*4882a593Smuzhiyun					};
609*4882a593Smuzhiyun				};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun				port@1 {
612*4882a593Smuzhiyun					reg = <1>;
613*4882a593Smuzhiyun					dp_altmode_mux: endpoint {
614*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
615*4882a593Smuzhiyun					};
616*4882a593Smuzhiyun				};
617*4882a593Smuzhiyun			};
618*4882a593Smuzhiyun		};
619*4882a593Smuzhiyun	};
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun	hym8563: hym8563@51 {
622*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
623*4882a593Smuzhiyun		reg = <0x51>;
624*4882a593Smuzhiyun		#clock-cells = <0>;
625*4882a593Smuzhiyun		clock-frequency = <32768>;
626*4882a593Smuzhiyun		clock-output-names = "hym8563";
627*4882a593Smuzhiyun		pinctrl-names = "default";
628*4882a593Smuzhiyun		pinctrl-0 = <&hym8563_int>;
629*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
630*4882a593Smuzhiyun		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
631*4882a593Smuzhiyun		wakeup-source;
632*4882a593Smuzhiyun		status = "okay";
633*4882a593Smuzhiyun	};
634*4882a593Smuzhiyun};
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun&mipi_dcphy0 {
637*4882a593Smuzhiyun	status = "okay";
638*4882a593Smuzhiyun};
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun&mipi_dcphy1 {
641*4882a593Smuzhiyun	status = "disabled";
642*4882a593Smuzhiyun};
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun&pdm0 {
645*4882a593Smuzhiyun	status = "okay";
646*4882a593Smuzhiyun};
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun&pcie2x1l1 {
649*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
650*4882a593Smuzhiyun	vpcie3v3-supply = <&vcc3v3_pcie20>;
651*4882a593Smuzhiyun	status = "okay";
652*4882a593Smuzhiyun};
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun&pcie2x1l2 {
655*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
656*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
657*4882a593Smuzhiyun	status = "okay";
658*4882a593Smuzhiyun};
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun&pinctrl {
661*4882a593Smuzhiyun	headphone {
662*4882a593Smuzhiyun		hp_det: hp-det {
663*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
664*4882a593Smuzhiyun		};
665*4882a593Smuzhiyun	};
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun	hym8563 {
668*4882a593Smuzhiyun		hym8563_int: hym8563-int {
669*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
670*4882a593Smuzhiyun		};
671*4882a593Smuzhiyun	};
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun	lcd {
674*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
675*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
676*4882a593Smuzhiyun		};
677*4882a593Smuzhiyun	};
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun	sensor {
680*4882a593Smuzhiyun		mpu6500_irq_gpio: mpu6500_irq_gpio {
681*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
682*4882a593Smuzhiyun		};
683*4882a593Smuzhiyun	};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun	touch {
686*4882a593Smuzhiyun		touch_gpio: touch-gpio {
687*4882a593Smuzhiyun			rockchip,pins =
688*4882a593Smuzhiyun				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
689*4882a593Smuzhiyun				<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
690*4882a593Smuzhiyun		};
691*4882a593Smuzhiyun	};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun	usb {
694*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
695*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
696*4882a593Smuzhiyun		};
697*4882a593Smuzhiyun	};
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun	usb-typec {
700*4882a593Smuzhiyun		usbc0_int: usbc0-int {
701*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
702*4882a593Smuzhiyun		};
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun		typec5v_pwren: typec5v-pwren {
705*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
706*4882a593Smuzhiyun		};
707*4882a593Smuzhiyun	};
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun	wireless-bluetooth {
710*4882a593Smuzhiyun		uart8_gpios: uart8-gpios {
711*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
712*4882a593Smuzhiyun		};
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
715*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
716*4882a593Smuzhiyun		};
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
719*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
720*4882a593Smuzhiyun		};
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun		bt_wake_host_irq: bt-wake-host-irq {
723*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
724*4882a593Smuzhiyun		};
725*4882a593Smuzhiyun	};
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun	wireless-wlan {
728*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
729*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
730*4882a593Smuzhiyun		};
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun		wifi_poweren_gpio: wifi-poweren-gpio {
733*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
734*4882a593Smuzhiyun		};
735*4882a593Smuzhiyun	};
736*4882a593Smuzhiyun};
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun&pwm11 {
739*4882a593Smuzhiyun	pinctrl-0 = <&pwm11m1_pins>;
740*4882a593Smuzhiyun	status = "okay";
741*4882a593Smuzhiyun};
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun&pwm13 {
744*4882a593Smuzhiyun	status = "okay";
745*4882a593Smuzhiyun	pinctrl-names = "active";
746*4882a593Smuzhiyun	pinctrl-0 = <&pwm13m1_pins>;
747*4882a593Smuzhiyun};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun&pwm15 {
750*4882a593Smuzhiyun	compatible = "rockchip,remotectl-pwm";
751*4882a593Smuzhiyun	pinctrl-names = "default";
752*4882a593Smuzhiyun	pinctrl-0 = <&pwm15m0_pins>;
753*4882a593Smuzhiyun	remote_pwm_id = <3>;
754*4882a593Smuzhiyun	handle_cpu_id = <1>;
755*4882a593Smuzhiyun	remote_support_psci = <0>;
756*4882a593Smuzhiyun	status = "okay";
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun	ir_key1 {
759*4882a593Smuzhiyun		rockchip,usercode = <0x4040>;
760*4882a593Smuzhiyun		rockchip,key_table =
761*4882a593Smuzhiyun			<0xf2   KEY_REPLY>,
762*4882a593Smuzhiyun			<0xba   KEY_BACK>,
763*4882a593Smuzhiyun			<0xf4   KEY_UP>,
764*4882a593Smuzhiyun			<0xf1   KEY_DOWN>,
765*4882a593Smuzhiyun			<0xef   KEY_LEFT>,
766*4882a593Smuzhiyun			<0xee   KEY_RIGHT>,
767*4882a593Smuzhiyun			<0xbd   KEY_HOME>,
768*4882a593Smuzhiyun			<0xea   KEY_VOLUMEUP>,
769*4882a593Smuzhiyun			<0xe3   KEY_VOLUMEDOWN>,
770*4882a593Smuzhiyun			<0xe2   KEY_SEARCH>,
771*4882a593Smuzhiyun			<0xb2   KEY_POWER>,
772*4882a593Smuzhiyun			<0xbc   KEY_MUTE>,
773*4882a593Smuzhiyun			<0xec   KEY_MENU>,
774*4882a593Smuzhiyun			<0xbf   0x190>,
775*4882a593Smuzhiyun			<0xe0   0x191>,
776*4882a593Smuzhiyun			<0xe1   0x192>,
777*4882a593Smuzhiyun			<0xe9   183>,
778*4882a593Smuzhiyun			<0xe6   248>,
779*4882a593Smuzhiyun			<0xe8   185>,
780*4882a593Smuzhiyun			<0xe7   186>,
781*4882a593Smuzhiyun			<0xf0   388>,
782*4882a593Smuzhiyun			<0xbe   0x175>;
783*4882a593Smuzhiyun	};
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun	ir_key2 {
786*4882a593Smuzhiyun		rockchip,usercode = <0xff00>;
787*4882a593Smuzhiyun		rockchip,key_table =
788*4882a593Smuzhiyun			<0xf9   KEY_HOME>,
789*4882a593Smuzhiyun			<0xbf   KEY_BACK>,
790*4882a593Smuzhiyun			<0xfb   KEY_MENU>,
791*4882a593Smuzhiyun			<0xaa   KEY_REPLY>,
792*4882a593Smuzhiyun			<0xb9   KEY_UP>,
793*4882a593Smuzhiyun			<0xe9   KEY_DOWN>,
794*4882a593Smuzhiyun			<0xb8   KEY_LEFT>,
795*4882a593Smuzhiyun			<0xea   KEY_RIGHT>,
796*4882a593Smuzhiyun			<0xeb   KEY_VOLUMEDOWN>,
797*4882a593Smuzhiyun			<0xef   KEY_VOLUMEUP>,
798*4882a593Smuzhiyun			<0xf7   KEY_MUTE>,
799*4882a593Smuzhiyun			<0xe7   KEY_POWER>,
800*4882a593Smuzhiyun			<0xfc   KEY_POWER>,
801*4882a593Smuzhiyun			<0xa9   KEY_VOLUMEDOWN>,
802*4882a593Smuzhiyun			<0xa8   KEY_PLAYPAUSE>,
803*4882a593Smuzhiyun			<0xe0   KEY_VOLUMEDOWN>,
804*4882a593Smuzhiyun			<0xa5   KEY_VOLUMEDOWN>,
805*4882a593Smuzhiyun			<0xab   183>,
806*4882a593Smuzhiyun			<0xb7   388>,
807*4882a593Smuzhiyun			<0xe8   388>,
808*4882a593Smuzhiyun			<0xf8   184>,
809*4882a593Smuzhiyun			<0xaf   185>,
810*4882a593Smuzhiyun			<0xed   KEY_VOLUMEDOWN>,
811*4882a593Smuzhiyun			<0xee   186>,
812*4882a593Smuzhiyun			<0xb3   KEY_VOLUMEDOWN>,
813*4882a593Smuzhiyun			<0xf1   KEY_VOLUMEDOWN>,
814*4882a593Smuzhiyun			<0xf2   KEY_VOLUMEDOWN>,
815*4882a593Smuzhiyun			<0xf3   KEY_SEARCH>,
816*4882a593Smuzhiyun			<0xb4   KEY_VOLUMEDOWN>,
817*4882a593Smuzhiyun			<0xa4   KEY_SETUP>,
818*4882a593Smuzhiyun			<0xbe   KEY_SEARCH>;
819*4882a593Smuzhiyun	};
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun	ir_key3 {
822*4882a593Smuzhiyun		rockchip,usercode = <0x1dcc>;
823*4882a593Smuzhiyun		rockchip,key_table =
824*4882a593Smuzhiyun			<0xee   KEY_REPLY>,
825*4882a593Smuzhiyun			<0xf0   KEY_BACK>,
826*4882a593Smuzhiyun			<0xf8   KEY_UP>,
827*4882a593Smuzhiyun			<0xbb   KEY_DOWN>,
828*4882a593Smuzhiyun			<0xef   KEY_LEFT>,
829*4882a593Smuzhiyun			<0xed   KEY_RIGHT>,
830*4882a593Smuzhiyun			<0xfc   KEY_HOME>,
831*4882a593Smuzhiyun			<0xf1   KEY_VOLUMEUP>,
832*4882a593Smuzhiyun			<0xfd   KEY_VOLUMEDOWN>,
833*4882a593Smuzhiyun			<0xb7   KEY_SEARCH>,
834*4882a593Smuzhiyun			<0xff   KEY_POWER>,
835*4882a593Smuzhiyun			<0xf3   KEY_MUTE>,
836*4882a593Smuzhiyun			<0xbf   KEY_MENU>,
837*4882a593Smuzhiyun			<0xf9   0x191>,
838*4882a593Smuzhiyun			<0xf5   0x192>,
839*4882a593Smuzhiyun			<0xb3   388>,
840*4882a593Smuzhiyun			<0xbe   KEY_1>,
841*4882a593Smuzhiyun			<0xba   KEY_2>,
842*4882a593Smuzhiyun			<0xb2   KEY_3>,
843*4882a593Smuzhiyun			<0xbd   KEY_4>,
844*4882a593Smuzhiyun			<0xf9   KEY_5>,
845*4882a593Smuzhiyun			<0xb1   KEY_6>,
846*4882a593Smuzhiyun			<0xfc   KEY_7>,
847*4882a593Smuzhiyun			<0xf8   KEY_8>,
848*4882a593Smuzhiyun			<0xb0   KEY_9>,
849*4882a593Smuzhiyun			<0xb6   KEY_0>,
850*4882a593Smuzhiyun			<0xb5   KEY_BACKSPACE>;
851*4882a593Smuzhiyun	};
852*4882a593Smuzhiyun};
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun&route_dsi0 {
855*4882a593Smuzhiyun	status = "okay";
856*4882a593Smuzhiyun	connect = <&vp3_out_dsi0>;
857*4882a593Smuzhiyun};
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun&route_dsi1 {
860*4882a593Smuzhiyun	status = "disabled";
861*4882a593Smuzhiyun	connect = <&vp3_out_dsi1>;
862*4882a593Smuzhiyun};
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun&sdmmc {
865*4882a593Smuzhiyun	status = "okay";
866*4882a593Smuzhiyun	vmmc-supply = <&vcc_3v3_sd_s0>;
867*4882a593Smuzhiyun};
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun&spdif_tx1 {
870*4882a593Smuzhiyun	status = "okay";
871*4882a593Smuzhiyun	pinctrl-names = "default";
872*4882a593Smuzhiyun	pinctrl-0 = <&spdif1m1_tx>;
873*4882a593Smuzhiyun};
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun&spdif_tx1_dc {
876*4882a593Smuzhiyun	status = "okay";
877*4882a593Smuzhiyun};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun&spdif_tx1_sound {
880*4882a593Smuzhiyun	status = "okay";
881*4882a593Smuzhiyun};
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun&spi2 {
884*4882a593Smuzhiyun	pinctrl-names = "default";
885*4882a593Smuzhiyun	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
886*4882a593Smuzhiyun	num-cs = <1>;
887*4882a593Smuzhiyun};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun&u2phy0_otg {
890*4882a593Smuzhiyun	rockchip,typec-vbus-det;
891*4882a593Smuzhiyun};
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun&u2phy2_host {
894*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
895*4882a593Smuzhiyun};
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun&u2phy3_host {
898*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
899*4882a593Smuzhiyun};
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun&uart8 {
902*4882a593Smuzhiyun	status = "okay";
903*4882a593Smuzhiyun	pinctrl-names = "default";
904*4882a593Smuzhiyun	pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>;
905*4882a593Smuzhiyun};
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun&usbdp_phy0 {
908*4882a593Smuzhiyun	orientation-switch;
909*4882a593Smuzhiyun	svid = <0xff01>;
910*4882a593Smuzhiyun	sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
911*4882a593Smuzhiyun	sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun	port {
914*4882a593Smuzhiyun		#address-cells = <1>;
915*4882a593Smuzhiyun		#size-cells = <0>;
916*4882a593Smuzhiyun		usbdp_phy0_orientation_switch: endpoint@0 {
917*4882a593Smuzhiyun			reg = <0>;
918*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
919*4882a593Smuzhiyun		};
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun		usbdp_phy0_dp_altmode_mux: endpoint@1 {
922*4882a593Smuzhiyun			reg = <1>;
923*4882a593Smuzhiyun			remote-endpoint = <&dp_altmode_mux>;
924*4882a593Smuzhiyun		};
925*4882a593Smuzhiyun	};
926*4882a593Smuzhiyun};
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun&usbdrd_dwc3_0 {
929*4882a593Smuzhiyun	usb-role-switch;
930*4882a593Smuzhiyun	port {
931*4882a593Smuzhiyun		#address-cells = <1>;
932*4882a593Smuzhiyun		#size-cells = <0>;
933*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
934*4882a593Smuzhiyun			reg = <0>;
935*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
936*4882a593Smuzhiyun		};
937*4882a593Smuzhiyun	};
938*4882a593Smuzhiyun};
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun&usbhost3_0 {
941*4882a593Smuzhiyun	status = "disabled";
942*4882a593Smuzhiyun};
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun&usbhost_dwc3_0 {
945*4882a593Smuzhiyun	status = "disabled";
946*4882a593Smuzhiyun};
947