xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7#include "rk3588s.dtsi"
8#include "rk3588s-evb.dtsi"
9#include "rk3588s-rk806-dual.dtsi"
10
11/ {
12	es7202_sound_micarray: es7202-sound-micarray {
13		status = "okay";
14		compatible = "simple-audio-card";
15		simple-audio-card,format = "i2s";
16		simple-audio-card,name = "rockchip,sound-micarray";
17		simple-audio-card,mclk-fs = <256>;
18		simple-audio-card,dai-link@0 {
19			format = "pdm";
20			cpu {
21				sound-dai = <&pdm0>;
22			};
23			codec {
24				sound-dai = <&es7202>;
25			};
26		};
27	};
28
29	es8388_sound: es8388-sound {
30		status = "okay";
31		compatible = "rockchip,multicodecs-card";
32		rockchip,card-name = "rockchip-es8388";
33		hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
34		io-channels = <&saradc 3>;
35		io-channel-names = "adc-detect";
36		keyup-threshold-microvolt = <1800000>;
37		poll-interval = <100>;
38		spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
39		hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
40		rockchip,format = "i2s";
41		rockchip,mclk-fs = <256>;
42		rockchip,cpu = <&i2s0_8ch>;
43		rockchip,codec = <&es8388>;
44		rockchip,audio-routing =
45			"Headphone", "LOUT1",
46			"Headphone", "ROUT1",
47			"Speaker", "LOUT2",
48			"Speaker", "ROUT2",
49			"Headphone", "Headphone Power",
50			"Headphone", "Headphone Power",
51			"Speaker", "Speaker Power",
52			"Speaker", "Speaker Power",
53			"LINPUT1", "Main Mic",
54			"LINPUT2", "Main Mic",
55			"RINPUT1", "Headset Mic",
56			"RINPUT2", "Headset Mic";
57		pinctrl-names = "default";
58		pinctrl-0 = <&hp_det>;
59		play-pause-key {
60			label = "playpause";
61			linux,code = <KEY_PLAYPAUSE>;
62			press-threshold-microvolt = <2000>;
63		};
64	};
65
66	vbus5v0_typec: vbus5v0-typec {
67		compatible = "regulator-fixed";
68		regulator-name = "vbus5v0_typec";
69		regulator-min-microvolt = <5000000>;
70		regulator-max-microvolt = <5000000>;
71		enable-active-high;
72		gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
73		vin-supply = <&vcc5v0_usb>;
74		pinctrl-names = "default";
75		pinctrl-0 = <&typec5v_pwren>;
76	};
77
78	vcc3v3_lcd_n: vcc3v3-lcd0-n {
79		compatible = "regulator-fixed";
80		regulator-name = "vcc3v3_lcd0_n";
81		regulator-boot-on;
82		enable-active-high;
83		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
84		vin-supply = <&vcc_1v8_s0>;
85	};
86
87	vcc5v0_u2host: vcc5v0-u2host {
88		compatible = "regulator-fixed";
89		regulator-name = "vcc5v0_u2host";
90		regulator-boot-on;
91		regulator-always-on;
92		regulator-min-microvolt = <5000000>;
93		regulator-max-microvolt = <5000000>;
94		enable-active-high;
95		gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
96		vin-supply = <&vcc5v0_usb>;
97		pinctrl-names = "default";
98		pinctrl-0 = <&vcc5v0_u2host_en>;
99	};
100
101	vcc5v0_u3host: vcc5v0-u3host {
102		compatible = "regulator-fixed";
103		regulator-name = "vcc5v0_u3host";
104		regulator-boot-on;
105		regulator-always-on;
106		regulator-min-microvolt = <5000000>;
107		regulator-max-microvolt = <5000000>;
108		enable-active-high;
109		gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
110		vin-supply = <&vcc5v0_usb>;
111		pinctrl-names = "default";
112		pinctrl-0 = <&vcc5v0_u3host_en>;
113	};
114};
115
116&backlight {
117	pwms = <&pwm7 0 25000 0>;
118	status = "okay";
119};
120
121&combphy0_ps {
122	status = "okay";
123};
124
125&combphy2_psu {
126	status = "okay";
127};
128
129&dp0 {
130	pinctrl-0 = <&dp0m2_pins>;
131	pinctrl-names = "default";
132	status = "okay";
133};
134
135&dp0_in_vp2 {
136	status = "okay";
137};
138
139/*
140 * mipi_dcphy0 needs to be enabled
141 * when dsi0 is enabled
142 */
143&dsi0 {
144	status = "disabled";
145};
146
147&dsi0_in_vp2 {
148	status = "disabled";
149};
150
151&dsi0_in_vp3 {
152	status = "disabled";
153};
154
155&dsi0_panel {
156	power-supply = <&vcc3v3_lcd_n>;
157
158	/*
159	 * because in hardware, the two screens share the reset pin,
160	 * so reset-gpios need only in dsi0 enable and dsi1 disabled
161	 * case.
162	 */
163	//reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
164	//pinctrl-names = "default";
165	//pinctrl-0 = <&lcd_rst_gpio>;
166	phy-c-option;
167	dsi,lanes  = <3>;
168
169	panel-init-sequence = [
170		23 00 02 FF 20
171		23 00 02 FB 01
172		23 00 02 05 D9
173		/* VGH=17V */
174		23 00 02 07 78
175		/* VGL=-14V */
176		23 00 02 08 5A
177		/* EN_VMODGATE2=1 */
178		23 00 02 0D 63
179		/* VGH=16V */
180		23 00 02 0E 91
181		/* VGL=-13V */
182		23 00 02 0F 73
183		/* GVDD=5.2V */
184		23 00 02 95 EB
185		23 00 02 96 EB
186		/* Disable VDDI LV */
187		23 00 02 30 11
188		/* ISOP */
189		23 00 02 6D 66
190		/* EN_GMACP */
191		23 00 02 75 A2
192		/* V128 */
193		23 00 02 77 3B
194		/* R(+) */
195		29 00 11 B0  00  08  00  23  00  4D  00  6D  00  89  00  A1  00  B6  00  C9
196		29 00 11 B1  00  DA  01  13  01  3C  01  7E  01  AB  01  F7  02  2F  02  31
197		29 00 11 B2  02  67  02  A6  02  D1  03  08  03  2E  03  5B  03  6B  03  7B
198		29 00 0D B3  03  8E  03  A2  03  B7  03  E7  03  FD  03  FF
199		/* G(+) */
200		29 00 11 B4  00  08  00  23  00  4D  00  6D  00  89  00  A1  00  B6  00  C9
201		29 00 11 B5  00  DA  01  13  01  3C  01  7E  01  AB  01  F7  02  2F  02  31
202		29 00 11 B6  02  67  02  A6  02  D1  03  08  03  2E  03  5B  03  6B  03  7B
203		29 00 0D B7  03  8E  03  A2  03  B7  03  E7  03  FD  03  FF
204		/* B(+) */
205		29 00 11 B8  00  08  00  23  00  4D  00  6D  00  89  00  A1  00  B6  00  C9
206		29 00 11 B9  00  DA  01  13  01  3C  01  7E  01  AB  01  F7  02  2F  02  31
207		29 00 11 BA  02  67  02  A6  02  D1  03  08  03  2E  03  5B  03  6B  03  7B
208		29 00 0D BB  03  8E  03  A2  03  B7  03  E7  03  FD  03  FF
209		/* CMD2_Page1 */
210		23 00 02 FF 21
211		23 00 02 FB 01
212		/* R(-) */
213		29 00 11 B0  00  00  00  1B  00  45  00  65  00  81  00  99  00  AE  00  C1
214		29 00 11 B1  00  D2  01  0B  01  34  01  76  01  A3  01  EF  02  27  02  29
215		29 00 11 B2  02  5F  02  9E  02  C9  03  00  03  26  03  53  03  63  03  73
216		29 00 0D B3  03  86  03  9A  03  AF  03  DF  03  F5  03  F7
217		/* G(-) */
218		29 00 11 B4  00  00  00  1B  00  45  00  65  00  81  00  99  00  AE  00  C1
219		29 00 11 B5  00  D2  01  0B  01  34  01  76  01  A3  01  EF  02  27  02  29
220		29 00 11 B6  02  5F  02  9E  02  C9  03  00  03  26  03  53  03  63  03  73
221		29 00 0D B7  03  86  03  9A  03  AF  03  DF  03  F5  03  F7
222		/* B(-) */
223		29 00 11 B8  00  00  00  1B  00  45  00  65  00  81  00  99  00  AE  00  C1
224		29 00 11 B9  00  D2  01  0B  01  34  01  76  01  A3  01  EF  02  27  02  29
225		29 00 11 BA  02  5F  02  9E  02  C9  03  00  03  26  03  53  03  63  03  73
226		29 00 0D BB  03  86  03  9A  03  AF  03  DF  03  F5  03  F7
227
228		29 00 02  FF 24
229		29 00 02  FB 01
230		/* VGL */
231		29 00 02 00 00
232		29 00 02 01 00
233		/* VDDO */
234		29 00 02 02 1C
235		29 00 02 03 1C
236		/* VDDE */
237		29 00 02 04 1D
238		29 00 02 05 1D
239		/* STV0 */
240		29 00 02 06 04
241		29 00 02 07 04
242		/* CLK8 */
243		29 00 02 08 0F
244		29 00 02 09 0F
245		/* CLK6 */
246		29 00 02 0A 0E
247		29 00 02 0B 0E
248		/* CLK4 */
249		29 00 02 0C 0D
250		29 00 02 0D 0D
251		/* CLK2 */
252		29 00 02 0E 0C
253		29 00 02 0F 0C
254		/* STV2 */
255		29 00 02 10 08
256		29 00 02 11 08
257
258		29 00 02 12 00
259		29 00 02 13 00
260		29 00 02 14 00
261		29 00 02 15 00
262		/* VGL */
263		29 00 02 16 00
264		29 00 02 17 00
265		/* VDDO */
266		29 00 02 18 1C
267		29 00 02 19 1C
268		/* VDDE */
269		29 00 02 1A 1D
270		29 00 02 1B 1D
271		/* STV0 */
272		29 00 02 1C 04
273		29 00 02 1D 04
274		/* CLK7 */
275		29 00 02 1E 0F
276		29 00 02 1F 0F
277		/* CLK5 */
278		29 00 02 20 0E
279		29 00 02 21 0E
280		/* CLK3 */
281		29 00 02 22 0D
282		29 00 02 23 0D
283		/* CLK1 */
284		29 00 02 24 0C
285		29 00 02 25 0C
286		/* STV1 */
287		29 00 02 26 08
288		29 00 02 27 08
289
290		29 00 02 28 00
291		29 00 02 29 00
292		29 00 02 2A 00
293		29 00 02 2B 00
294		/* STV0 */
295		29 00 02 2D 20
296		29 00 02 2F 0A
297		29 00 02 30 44
298		29 00 02 33 0C
299		29 00 02 34 32
300
301		29 00 02 37 44
302		29 00 02 38 40
303		29 00 02 39 00
304		29 00 02 3A 50
305		29 00 02 3B 50
306		29 00 02 3D 42
307		/* STV */
308		29 00 02 3F 06
309		29 00 02 43 06
310
311		29 00 02 47 66
312		29 00 02 4A 50
313		29 00 02 4B 50
314		29 00 02 4C 91
315		/* GCK */
316		29 00 02 4D 21
317		29 00 02 4E 43
318		29 00 02 51 12
319		29 00 02 52 34
320		29 00 03 55 82 02
321		29 00 02 56 04
322		29 00 02 58 21
323		29 00 02 59 30
324		29 00 02 5A 50
325		29 00 02 5B 50
326		29 00 03 5E 00 06
327		29 00 02 5F 00
328		/* EN_LFD_SOURCE=0 */
329		29 00 02 65 82
330		/* VDDO, VDDE */
331		29 00 02 7E 20
332		29 00 02 7F 3C
333		29 00 02 82 04
334		29 00 02 97 C0
335
336		29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00
337		/* qclk=96/5 Mhz */
338		29 00 02 91 44
339		29 00 02 92 55
340		29 00 02 93 1A
341		29 00 02 94 5F
342		/* SOG_HBP */
343		29 00 02 D7 55
344		29 00 02 DA 0A
345		29 00 02 DE 08
346		/* Normal */
347		29 00 02 DB 05
348		29 00 02 DC 55
349		29 00 02 DD 22
350		/* Line N */
351		29 00 02 DF 05
352		29 00 02 E0 55
353		/* Line N+1 */
354		29 00 02 E1 05
355		29 00 02 E2 55
356		/* TP0 */
357		29 00 02 E3 05
358		29 00 02 E4 55
359		/* TP3 */
360		29 00 02 E5 05
361		29 00 02 E6 55
362		/* Gate EQ */
363		29 00 02 5C 00
364		29 00 02 5D 00
365		/* TP3 */
366		29 00 02 8D 00
367		29 00 02 8E 00
368		/* No Sync @ TP */
369		29 00 02 B5 90
370
371		29 00 02 FF 25
372		29 00 02 FB 01
373		/* disable auto_vbp_vfp */
374		29 00 02 05 00
375		/* ESD_DET_ERR_SEL */
376		29 00 02 19 07
377		/* DP_N_GCK */
378		29 00 02 1F 50
379		29 00 02 20 50
380		/* DP_N_1_GCK */
381		29 00 02 26 50
382		29 00 02 27 50
383		/* TP0_GCK */
384		29 00 02 33 50
385		29 00 02 34 50
386		/* TP3 GCK/MUX=1 */
387		29 00 02 3F E0
388		/* TP3_GCK_START_LINE */
389		29 00 02 40 00
390		/* TP3_STV */
391		29 00 02 44 00
392		29 00 02 45 40
393		/* TP3_GCK */
394		29 00 02 48 50
395		29 00 02 49 50
396		/* LSTP0 */
397		29 00 02 5B 00
398		29 00 02 5C 00
399		29 00 02 5D 00
400		29 00 02 5E D0
401
402		29 00 02 61 50
403		29 00 02 62 50
404		/* en_vfp_addvsync */
405		29 00 02 F1 10
406		/* CMD2,Page10 */
407		29 00 02 FF 2A
408		29 00 02 FB 01
409		/* PWRONOFF */
410		/* STV */
411		29 00 02 64 16
412		/* CLR */
413		29 00 02 67 16
414		/* GCK */
415		29 00 02 6A 16
416		/* POL */
417		29 00 02 70 30
418		/* ABOFF */
419		29 00 02 A2 F3
420		29 00 02 A3 FF
421		29 00 02 A4 FF
422		29 00 02 A5 FF
423		/* Long_V_TIMING disable */
424		29 00 02 D6 08
425		/* CMD2,Page6 */
426		29 00 02 FF 26
427		29 00 02 FB 01
428		/* TPEN */
429		29 00 02 00 81
430		/* 90Hz */
431		29 00 02 01 30
432
433		29 00 02 02 31
434		29 00 02 0A F2
435		//Table A (90Hz)
436		29 00 02 04 28
437		29 00 02 06 3C
438		29 00 02 0C 0B
439		29 00 02 0D 0C
440		29 00 02 0F 00
441		29 00 02 11 00
442		29 00 02 12 50
443		29 00 02 13 AE
444		29 00 02 14 A6
445		29 00 02 16 10
446		29 00 02 19 08
447		29 00 02 1A FF
448		29 00 02 1B 08
449		29 00 02 1C 80
450		29 00 02 22 00
451		29 00 02 23 00
452		29 00 02 2A 08
453		29 00 02 2B FF
454
455		29 00 02 1D 00
456		29 00 02 1E 55
457		29 00 02 1F 55
458		29 00 02 24 00
459		29 00 02 25 55
460		29 00 02 2F 05
461		29 00 02 30 55
462		29 00 02 31 05
463		29 00 02 32 6D
464		29 00 02 39 00
465		29 00 02 3A 55
466		/* Table B (60Hz,81*1+101*19=2000, Extra=20) */
467		29 00 02 8B 28
468		29 00 02 8C 13
469		29 00 02 8D 0A
470		29 00 02 8F 0A
471		29 00 02 91 00
472		29 00 02 92 50
473		29 00 02 93 51
474		29 00 02 94 65
475		29 00 02 96 10
476		29 00 02 99 0A
477		29 00 02 9A 7F
478		29 00 02 9B 0A
479		29 00 02 9C 0C
480		29 00 02 9D 0A
481		29 00 02 9E 7F
482
483		29 00 02 3F 00
484		29 00 02 40 75
485		29 00 02 41 75
486		29 00 02 42 75
487		29 00 02 43 00
488		29 00 02 44 75
489		29 00 02 45 05
490		29 00 02 46 75
491		29 00 02 47 05
492		29 00 02 48 8D
493		29 00 02 49 00
494		29 00 02 4A 75
495		/* STV0 */
496		29 00 02 4D 5D
497		29 00 02 4E 60
498		/* STV */
499		29 00 02 4F 5D
500		29 00 02 50 60
501		/* GCK */
502		29 00 02 51 70
503		29 00 02 52 60
504		/* DP_N_GCK */
505		29 00 02 56 70
506		29 00 02 58 60
507		/* DP_N_1_GCK */
508		29 00 02 5B 70
509		29 00 02 5C 60
510		/* TP0_GCK */
511		29 00 02 60 70
512		29 00 02 61 60
513		/* TP3_GCK */
514		29 00 02 64 70
515		29 00 02 65 60
516		/* LSTP0 */
517		29 00 02 72 70
518		29 00 02 73 60
519		/* PRZ1 */
520		29 00 02 20 01
521		/* PRZ3 */
522		/* Rescan=3 */
523		29 00 02 33 11
524		29 00 02 34 78
525		29 00 02 35 16
526		/* DLH */
527		29 00 02 C8 04
528		29 00 02 C9 80
529		29 00 02 CA 4E
530		29 00 02 CB 00
531		29 00 02 A9 4C
532		29 00 02 AA 47
533		/* CMD2,Page7 */
534		29 00 02 FF 27
535		29 00 02 FB 01
536		/* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */
537		29 00 02 56 06
538		/* FR0(60Hz) */
539		29 00 02 58 80
540		29 00 02 59 53
541		29 00 02 5A 00
542		29 00 02 5B 14
543		29 00 02 5C 00
544		29 00 02 5D 01
545		29 00 02 5E 20
546		29 00 02 5F 10
547		29 00 02 60 00
548		29 00 02 61 1D
549		29 00 02 62 00
550		29 00 02 63 01
551		29 00 02 64 24
552		29 00 02 65 1C
553		29 00 02 66 00
554		29 00 02 67 01
555		29 00 02 68 25
556		/* FR1(90Hz) */
557		29 00 02 78 80
558		29 00 02 79 73
559		29 00 02 7A 00
560		29 00 02 7B 14
561		29 00 02 7C 00
562		29 00 02 7D 02
563		29 00 02 7E 20
564		29 00 02 7F 21
565		29 00 02 80 00
566		29 00 02 81 2A
567		29 00 02 82 00
568		29 00 02 83 01
569		29 00 02 84 1C
570		29 00 02 85 28
571		29 00 02 86 00
572		29 00 02 87 01
573		29 00 02 88 1D
574
575		29 00 02 00 00
576		29 00 02 C3 00
577		/* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */
578		29 00 02 D1 24
579		29 00 02 D2 53
580		/* CMD2,Page10 */
581		29 00 02 FF 2A
582		29 00 02 FB 01
583		29 00 02 01 05
584		29 00 02 02 55
585		/* TP0 */
586		29 00 02 03 05
587		29 00 02 04 75
588		/* TP3 */
589		29 00 02 05 05
590		29 00 02 06 75
591		/* PEN_EN=1, UL_FREQ=0 */
592		29 00 02 22 2F
593		/* 90Hz */
594		29 00 02 23 11
595		/* FR0 (60Hz) */
596		29 00 02 24 00
597		29 00 02 25 75
598		29 00 02 27 00
599		29 00 02 28 1A
600		29 00 02 29 00
601		29 00 02 2A 1A
602		29 00 02 2B 00
603		29 00 02 2D 1A
604		/* FR1 (90Hz) */
605		29 00 02 2F 00
606		29 00 02 30 55
607		29 00 02 32 00
608		29 00 02 33 1A
609		29 00 02 34 00
610		29 00 02 35 1A
611		29 00 02 36 00
612		29 00 02 37 1A
613		/* CMD2,Page3 */
614		29 00 02 FF 23
615		29 00 02 FB 01
616		/* DBV=12 bit */
617		29 00 02 00 80
618		/* PWM frequency */
619		29 00 02 07 00
620		/* CMD3,PageA */
621		29 00 02 FF E0
622		29 00 02 FB 01
623		/* VCOM Driving Ability */
624		29 00 02 14 60
625		29 00 02 16 C0
626		/* CMD3,PageB */
627		29 00 02 FF F0
628		29 00 02 FB 01
629		/* slave osc workaround */
630		29 00 02 3A 08
631		/* CMD3,PageC */
632		29 00 02 FF D0
633		29 00 02 FB 01
634		29 00 02 1C 88
635		29 00 02 1D 08
636		/* CMD1 */
637		29 00 02 FF 10
638		29 00 02 FB 01
639		/* Only Write Slave */
640		29 00 02 B9 01
641		/* CMD2,Page0 */
642		29 00 02 FF 20
643		29 00 02 FB 01
644		29 00 02 18 40
645		/* CMD1 */
646		29 00 02 FF 10
647		29 00 02 FB 01
648		/* Write Master & Slave */
649		29 00 02 B9 02
650		29 00 02 35 00
651		29 00 03 51 00 FF
652		29 00 02 53 24
653		29 00 02 55 00
654		29 00 02 BB 13
655		/* VBP+VFP=121 */
656		29 00 06 3B 03 5F 1A 04 04
657		/* CMD2,Page5 */
658		29 00 02 FF 25
659		/* FRM */
660		29 00 02 EC 00
661		/* CMD1 */
662		29 00 02 FF 10
663		29 00 02 FB 01
664		05 FF 01 11
665		05 FF 01 29
666	];
667
668	panel-exit-sequence = [
669		05 00 01 28
670		05 00 01 10
671	];
672
673	disp_timings0: display-timings {
674		native-mode = <&dsi0_timing0>;
675		dsi0_timing0: timing0 {
676			clock-frequency = <241300000>;
677			hactive = <1200>;
678			vactive = <2000>;
679			hfront-porch = <31>;
680			hsync-len = <4>;
681			hback-porch = <32>;
682			vfront-porch = <26>;
683			vsync-len = <2>;
684			vback-porch = <93>;
685			hsync-active = <0>;
686			vsync-active = <0>;
687			de-active = <0>;
688			pixelclk-active = <0>;
689		};
690	};
691};
692
693/*
694 * mipi_dcphy1 needs to be enabled
695 * when dsi1 is enabled
696 */
697&dsi1 {
698	status = "okay";
699};
700
701&dsi1_in_vp2 {
702	status = "disabled";
703};
704
705&dsi1_in_vp3 {
706	status = "okay";
707};
708
709&dsi1_panel {
710	power-supply = <&vcc3v3_lcd_n>;
711
712	reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
713	pinctrl-names = "default";
714	pinctrl-0 = <&lcd_rst_gpio>;
715};
716
717&hdmi0 {
718	enable-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
719	status = "okay";
720};
721
722&hdmi0_in_vp0 {
723	status = "okay";
724};
725
726&hdmi0_sound {
727	status = "okay";
728};
729
730&hdptxphy_hdmi0 {
731	status = "okay";
732};
733
734&i2c2 {
735	status = "okay";
736
737	hym8563: hym8563@51 {
738		compatible = "haoyu,hym8563";
739		reg = <0x51>;
740		#clock-cells = <0>;
741		clock-frequency = <32768>;
742		clock-output-names = "hym8563";
743		pinctrl-names = "default";
744		pinctrl-0 = <&hym8563_int>;
745		interrupt-parent = <&gpio0>;
746		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
747		wakeup-source;
748	};
749};
750
751&i2c5 {
752	status = "okay";
753
754	ls_stk3332: light@47 {
755		compatible = "ls_stk3332";
756		status = "disabled";
757		reg = <0x47>;
758		type = <SENSOR_TYPE_LIGHT>;
759		irq_enable = <0>;
760		als_threshold_high = <100>;
761		als_threshold_low = <10>;
762		als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */
763		poll_delay_ms = <100>;
764	};
765
766	ps_stk3332: proximity@47 {
767		compatible = "ps_stk3332";
768		status = "disabled";
769		reg = <0x47>;
770		type = <SENSOR_TYPE_PROXIMITY>;
771		//pinctrl-names = "default";
772		//pinctrl-0 = <&gpio3_c6>;
773		//irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
774		//irq_enable = <1>;
775		ps_threshold_high = <0x200>;
776		ps_threshold_low = <0x100>;
777		ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */
778		ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/
779		poll_delay_ms = <100>;
780	};
781
782	mpu6500_acc: mpu_acc@68 {
783		compatible = "mpu6500_acc";
784		reg = <0x68>;
785		irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>;
786		irq_enable = <0>;
787		poll_delay_ms = <30>;
788		type = <SENSOR_TYPE_ACCEL>;
789		layout = <8>;
790	};
791
792	mpu6500_gyro: mpu_gyro@68 {
793		compatible = "mpu6500_gyro";
794		reg = <0x68>;
795		irq_enable = <0>;
796		poll_delay_ms = <30>;
797		type = <SENSOR_TYPE_GYROSCOPE>;
798		layout = <8>;
799	};
800};
801
802&i2c6 {
803	status = "okay";
804	pinctrl-names = "default";
805	pinctrl-0 = <&i2c6m3_xfer>;
806
807	gt1x: gt1x@14 {
808		compatible = "goodix,gt1x";
809		reg = <0x14>;
810		pinctrl-names = "default";
811		pinctrl-0 = <&touch_gpio>;
812		goodix,rst-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
813		goodix,irq-gpio = <&gpio4 RK_PB4 IRQ_TYPE_LEVEL_LOW>;
814		power-supply = <&vcc3v3_lcd_n>;
815	};
816};
817
818&i2c3 {
819	status = "okay";
820
821	es8388: es8388@11 {
822		status = "okay";
823		#sound-dai-cells = <0>;
824		compatible = "everest,es8388", "everest,es8323";
825		reg = <0x11>;
826		clocks = <&mclkout_i2s0>;
827		clock-names = "mclk";
828		assigned-clocks = <&mclkout_i2s0>;
829		assigned-clock-rates = <12288000>;
830		pinctrl-names = "default";
831		pinctrl-0 = <&i2s0_mclk>;
832	};
833
834	es7202: es7202@32 {
835		status = "okay";
836		#sound-dai-cells = <0>;
837		compatible = "ES7202_PDM_ADC_1";
838		power-supply = <&vcc_1v8_s0>;	/* only 1v8 or 3v3, default is 3v3 */
839		reg = <0x32>;
840	};
841};
842
843&i2s5_8ch {
844	status = "okay";
845};
846
847&mipi_dcphy0 {
848	status = "disabled";
849};
850
851&mipi_dcphy1 {
852	status = "okay";
853};
854
855&sdmmc {
856	status = "okay";
857	vmmc-supply = <&vcc_3v3_sd_s0>;
858};
859
860&pdm0 {
861	status = "okay";
862};
863
864&pinctrl {
865	headphone {
866		hp_det: hp-det {
867			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
868		};
869	};
870
871	hym8563 {
872		hym8563_int: hym8563-int {
873			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
874		};
875	};
876
877	lcd {
878		lcd_rst_gpio: lcd-rst-gpio {
879			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
880		};
881	};
882
883	sensor {
884		mpu6500_irq_gpio: mpu6500_irq_gpio {
885			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
886		};
887	};
888
889	touch {
890		touch_gpio: touch-gpio {
891			rockchip,pins =
892				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
893				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
894		};
895	};
896
897	usb {
898		typec5v_pwren: typec5v-pwren {
899			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
900		};
901
902		vcc5v0_u2host_en: vcc5v0-u2host-en {
903			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
904		};
905
906		vcc5v0_u3host_en: vcc5v0-u3host-en {
907			rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
908		};
909	};
910};
911
912&pwm7 {
913	status = "okay";
914};
915
916&route_dsi0 {
917	status = "disabled";
918	connect = <&vp3_out_dsi0>;
919};
920
921&route_dsi1 {
922	status = "okay";
923	connect = <&vp3_out_dsi1>;
924};
925
926&sata0 {
927	status = "okay";
928};
929
930&u2phy0_otg {
931	vbus-supply = <&vbus5v0_typec>;
932};
933
934&u2phy2_host {
935	phy-supply = <&vcc5v0_u2host>;
936};
937
938&u2phy3_host {
939	phy-supply = <&vcc5v0_u3host>;
940};
941
942&usbdp_phy0 {
943	rockchip,dp-lane-mux = <0 1 2 3>;
944};
945
946&usbdrd_dwc3_0 {
947	dr_mode = "otg";
948	phys = <&u2phy0_otg>;
949	phy-names = "usb2-phy";
950	maximum-speed = "high-speed";
951	extcon = <&u2phy0>;
952};
953