xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588-vehicle-s66-v10.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "rk3588m.dtsi"
8*4882a593Smuzhiyun#include "rk3588-vehicle-s66.dtsi"
9*4882a593Smuzhiyun#include "rk3588-rk806-dual.dtsi"
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	pcie20_avdd0v85: pcie20-avdd0v85 {
12*4882a593Smuzhiyun		compatible = "regulator-fixed";
13*4882a593Smuzhiyun		regulator-name = "pcie20_avdd0v85";
14*4882a593Smuzhiyun		regulator-boot-on;
15*4882a593Smuzhiyun		regulator-always-on;
16*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
17*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
18*4882a593Smuzhiyun		vin-supply = <&vdd_0v85_s0>;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	pcie20_avdd1v8: pcie20-avdd1v8 {
22*4882a593Smuzhiyun		compatible = "regulator-fixed";
23*4882a593Smuzhiyun		regulator-name = "pcie20_avdd1v8";
24*4882a593Smuzhiyun		regulator-boot-on;
25*4882a593Smuzhiyun		regulator-always-on;
26*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
27*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
28*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	pcie30_avdd0v75: pcie30-avdd0v75 {
32*4882a593Smuzhiyun		compatible = "regulator-fixed";
33*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v75";
34*4882a593Smuzhiyun		regulator-boot-on;
35*4882a593Smuzhiyun		regulator-always-on;
36*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
37*4882a593Smuzhiyun		regulator-max-microvolt = <750000>;
38*4882a593Smuzhiyun		vin-supply = <&avdd_0v75_s0>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
42*4882a593Smuzhiyun		compatible = "regulator-fixed";
43*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
44*4882a593Smuzhiyun		regulator-boot-on;
45*4882a593Smuzhiyun		regulator-always-on;
46*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
47*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
48*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
52*4882a593Smuzhiyun		compatible = "regulator-fixed";
53*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
54*4882a593Smuzhiyun		regulator-boot-on;
55*4882a593Smuzhiyun		regulator-always-on;
56*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
57*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
58*4882a593Smuzhiyun		enable-active-high;
59*4882a593Smuzhiyun		//gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
61*4882a593Smuzhiyun		//pinctrl-names = "default";
62*4882a593Smuzhiyun		//pinctrl-0 = <&vcc5v0_host_en>;
63*4882a593Smuzhiyun		//TODO: should powered by MCU
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun&combphy0_ps {
68*4882a593Smuzhiyun	status = "okay";
69*4882a593Smuzhiyun};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun&combphy1_ps {
72*4882a593Smuzhiyun	status = "okay";
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&combphy2_psu {
76*4882a593Smuzhiyun	status = "okay";
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&gmac0 {
80*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
81*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
82*4882a593Smuzhiyun	clock_in_out = "output";
83*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
84*4882a593Smuzhiyun	snps,reset-active-low;
85*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
86*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
87*4882a593Smuzhiyun	pinctrl-0 = <&gmac0_miim
88*4882a593Smuzhiyun		     &gmac0_tx_bus2
89*4882a593Smuzhiyun		     &gmac0_rx_bus2
90*4882a593Smuzhiyun		     &gmac0_rgmii_clk
91*4882a593Smuzhiyun		     &gmac0_rgmii_bus>;
92*4882a593Smuzhiyun	tx_delay = <0x43>;
93*4882a593Smuzhiyun	//rx_delay = <0x3f>;
94*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
95*4882a593Smuzhiyun	status = "okay";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&i2c3 {
99*4882a593Smuzhiyun	status = "okay";
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun	iam20680_acc: acc@69 {
102*4882a593Smuzhiyun		compatible = "iam20680_acc";
103*4882a593Smuzhiyun		reg = <0x69>;
104*4882a593Smuzhiyun		irq-gpio = <&gpio1 RK_PC2 IRQ_TYPE_LEVEL_LOW>;
105*4882a593Smuzhiyun		irq_enable = <1>;
106*4882a593Smuzhiyun		poll_delay_ms = <30>;
107*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
108*4882a593Smuzhiyun		layout = <1>;
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	iam20680_gyro: gyro@69 {
112*4882a593Smuzhiyun		compatible = "iam20680_gyro";
113*4882a593Smuzhiyun		reg = <0x69>;
114*4882a593Smuzhiyun		irq_enable = <0>;
115*4882a593Smuzhiyun		poll_delay_ms = <30>;
116*4882a593Smuzhiyun		type = <SENSOR_TYPE_GYROSCOPE>;
117*4882a593Smuzhiyun		layout = <1>;
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun	//todo, add mfi
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&i2c4 {
124*4882a593Smuzhiyun	status = "okay";
125*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m0_xfer>;
126*4882a593Smuzhiyun	//todo, add LT9211
127*4882a593Smuzhiyun};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun&mdio0 {
130*4882a593Smuzhiyun	rgmii_phy: phy@1 {
131*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
132*4882a593Smuzhiyun		reg = <0x1>;
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&pcie2x1l0 {
137*4882a593Smuzhiyun	status = "disabled";
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&pcie2x1l1 {
141*4882a593Smuzhiyun	status = "disabled";
142*4882a593Smuzhiyun};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun&pcie2x1l2 {
145*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&pcie30phy {
150*4882a593Smuzhiyun	rockchip,pcie30-phymode = <PHY_MODE_PCIE_NABIBI>;
151*4882a593Smuzhiyun	status = "disabled";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&pcie3x4 {
155*4882a593Smuzhiyun	num-lanes = <1>;
156*4882a593Smuzhiyun	status = "disabled";
157*4882a593Smuzhiyun};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun&sata0 {
160*4882a593Smuzhiyun	status = "disabled";
161*4882a593Smuzhiyun};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun&sdmmc {
164*4882a593Smuzhiyun	status = "disabled";
165*4882a593Smuzhiyun};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun&u2phy1_otg {
168*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
169*4882a593Smuzhiyun};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun&u2phy2_host {
172*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
173*4882a593Smuzhiyun};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun&u2phy3_host {
176*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&usbdp_phy0 {
180*4882a593Smuzhiyun	rockchip,dp-lane-mux = <2 3>;
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&usbdp_phy0_dp {
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&usbdp_phy0_u3 {
189*4882a593Smuzhiyun	status = "okay";
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&usbdp_phy1 {
193*4882a593Smuzhiyun	rockchip,dp-lane-mux = <3 2 1 0>;
194*4882a593Smuzhiyun	status = "disabled";
195*4882a593Smuzhiyun};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun&usbdp_phy1_dp {
198*4882a593Smuzhiyun	status = "disabled";
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&usbdp_phy1_u3 {
202*4882a593Smuzhiyun	maximum-speed = "high-speed";
203*4882a593Smuzhiyun	status = "okay";
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&usbdrd_dwc3_0 {
207*4882a593Smuzhiyun	dr_mode = "peripheral";
208*4882a593Smuzhiyun	maximum-speed = "high-speed";
209*4882a593Smuzhiyun	extcon = <&u2phy0>;
210*4882a593Smuzhiyun	status = "okay";
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&usbdrd_dwc3_1 {
214*4882a593Smuzhiyun	dr_mode = "host";
215*4882a593Smuzhiyun	maximum-speed = "high-speed";
216*4882a593Smuzhiyun	snps,dis_u2_susphy_quirk;
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219