1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "rk3588m.dtsi" 8#include "rk3588-vehicle-s66.dtsi" 9#include "rk3588-rk806-dual.dtsi" 10/ { 11 pcie20_avdd0v85: pcie20-avdd0v85 { 12 compatible = "regulator-fixed"; 13 regulator-name = "pcie20_avdd0v85"; 14 regulator-boot-on; 15 regulator-always-on; 16 regulator-min-microvolt = <850000>; 17 regulator-max-microvolt = <850000>; 18 vin-supply = <&vdd_0v85_s0>; 19 }; 20 21 pcie20_avdd1v8: pcie20-avdd1v8 { 22 compatible = "regulator-fixed"; 23 regulator-name = "pcie20_avdd1v8"; 24 regulator-boot-on; 25 regulator-always-on; 26 regulator-min-microvolt = <1800000>; 27 regulator-max-microvolt = <1800000>; 28 vin-supply = <&avcc_1v8_s0>; 29 }; 30 31 pcie30_avdd0v75: pcie30-avdd0v75 { 32 compatible = "regulator-fixed"; 33 regulator-name = "pcie30_avdd0v75"; 34 regulator-boot-on; 35 regulator-always-on; 36 regulator-min-microvolt = <750000>; 37 regulator-max-microvolt = <750000>; 38 vin-supply = <&avdd_0v75_s0>; 39 }; 40 41 pcie30_avdd1v8: pcie30-avdd1v8 { 42 compatible = "regulator-fixed"; 43 regulator-name = "pcie30_avdd1v8"; 44 regulator-boot-on; 45 regulator-always-on; 46 regulator-min-microvolt = <1800000>; 47 regulator-max-microvolt = <1800000>; 48 vin-supply = <&avcc_1v8_s0>; 49 }; 50 51 vcc5v0_host: vcc5v0-host { 52 compatible = "regulator-fixed"; 53 regulator-name = "vcc5v0_host"; 54 regulator-boot-on; 55 regulator-always-on; 56 regulator-min-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>; 58 enable-active-high; 59 //gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; 60 vin-supply = <&vcc5v0_usb>; 61 //pinctrl-names = "default"; 62 //pinctrl-0 = <&vcc5v0_host_en>; 63 //TODO: should powered by MCU 64 }; 65}; 66 67&combphy0_ps { 68 status = "okay"; 69}; 70 71&combphy1_ps { 72 status = "okay"; 73}; 74 75&combphy2_psu { 76 status = "okay"; 77}; 78 79&gmac0 { 80 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 81 phy-mode = "rgmii-rxid"; 82 clock_in_out = "output"; 83 snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; 84 snps,reset-active-low; 85 /* Reset time is 20ms, 100ms for rtl8211f */ 86 snps,reset-delays-us = <0 20000 100000>; 87 pinctrl-0 = <&gmac0_miim 88 &gmac0_tx_bus2 89 &gmac0_rx_bus2 90 &gmac0_rgmii_clk 91 &gmac0_rgmii_bus>; 92 tx_delay = <0x43>; 93 //rx_delay = <0x3f>; 94 phy-handle = <&rgmii_phy>; 95 status = "okay"; 96}; 97 98&i2c3 { 99 status = "okay"; 100 101 iam20680_acc: acc@69 { 102 compatible = "iam20680_acc"; 103 reg = <0x69>; 104 irq-gpio = <&gpio1 RK_PC2 IRQ_TYPE_LEVEL_LOW>; 105 irq_enable = <1>; 106 poll_delay_ms = <30>; 107 type = <SENSOR_TYPE_ACCEL>; 108 layout = <1>; 109 }; 110 111 iam20680_gyro: gyro@69 { 112 compatible = "iam20680_gyro"; 113 reg = <0x69>; 114 irq_enable = <0>; 115 poll_delay_ms = <30>; 116 type = <SENSOR_TYPE_GYROSCOPE>; 117 layout = <1>; 118 }; 119 120 //todo, add mfi 121}; 122 123&i2c4 { 124 status = "okay"; 125 pinctrl-0 = <&i2c4m0_xfer>; 126 //todo, add LT9211 127}; 128 129&mdio0 { 130 rgmii_phy: phy@1 { 131 compatible = "ethernet-phy-ieee802.3-c22"; 132 reg = <0x1>; 133 }; 134}; 135 136&pcie2x1l0 { 137 status = "disabled"; 138}; 139 140&pcie2x1l1 { 141 status = "disabled"; 142}; 143 144&pcie2x1l2 { 145 rockchip,skip-scan-in-resume; 146 status = "okay"; 147}; 148 149&pcie30phy { 150 rockchip,pcie30-phymode = <PHY_MODE_PCIE_NABIBI>; 151 status = "disabled"; 152}; 153 154&pcie3x4 { 155 num-lanes = <1>; 156 status = "disabled"; 157}; 158 159&sata0 { 160 status = "disabled"; 161}; 162 163&sdmmc { 164 status = "disabled"; 165}; 166 167&u2phy1_otg { 168 phy-supply = <&vcc5v0_host>; 169}; 170 171&u2phy2_host { 172 phy-supply = <&vcc5v0_host>; 173}; 174 175&u2phy3_host { 176 phy-supply = <&vcc5v0_host>; 177}; 178 179&usbdp_phy0 { 180 rockchip,dp-lane-mux = <2 3>; 181 status = "okay"; 182}; 183 184&usbdp_phy0_dp { 185 status = "okay"; 186}; 187 188&usbdp_phy0_u3 { 189 status = "okay"; 190}; 191 192&usbdp_phy1 { 193 rockchip,dp-lane-mux = <3 2 1 0>; 194 status = "disabled"; 195}; 196 197&usbdp_phy1_dp { 198 status = "disabled"; 199}; 200 201&usbdp_phy1_u3 { 202 maximum-speed = "high-speed"; 203 status = "okay"; 204}; 205 206&usbdrd_dwc3_0 { 207 dr_mode = "peripheral"; 208 maximum-speed = "high-speed"; 209 extcon = <&u2phy0>; 210 status = "okay"; 211}; 212 213&usbdrd_dwc3_1 { 214 dr_mode = "host"; 215 maximum-speed = "high-speed"; 216 snps,dis_u2_susphy_quirk; 217 status = "okay"; 218}; 219